Help for PLL loop simulation

[wensi]

I use .tran analysis to run a pll ,the loop locked in TT and FF corner,but it locked to a wrong frequency(may be not lock indeed,but the LPF voltage looks like the loop have locked ) in SS corner,I have resimulated sereral times,but the results are alway the same ,who can give me some suggestions?

Thanks

 

[sunking]

Does the VCO range is right?
Check the controlled voltage of VCO.

 

[tfwee]

Does your LPF Voltage match your tuning voltage of your VCO at SS Corner. You should have a plot of your control voltage of your VCO verus the control voltage at different corner. Check whether it match the VCO characteristics. Another point to check is your linear range of your charge pump output voltage. Maybe it already hit the limit, which give you a false impression that the loop is locked.

 

[wensi]

Thanks for your reply ! The VCO range can cover the pll output range, the pll should locked to 2.2V according to the separete vco simulation results,but the pll locked to 1.85V,in this case I check the reference input and the feedback signal,the two pulse phase are different ,but the vco control voltage never changed,and the waveform looks like the pll has locked,I don't know why this happencd!