dudleyzty
Junior Member level 2
I try to combine two group of VHDL project to one project, every individual project can be compliled and simulated OK, but the combined
project cannot be simulated correctly, it can be compiled OK.
The two project have no common signal, they're all independent.
PLS help me!
project cannot be simulated correctly, it can be compiled OK.
The two project have no common signal, they're all independent.
PLS help me!