Help finding a digital counter architecture

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Is it possible to make a digital ripple counter out of 6T SRAM cells? I’m trying to make the most area compact architecture I can find. I need to have asynchronous reset capabilities and the ability to latch each output value without interfering with counting. Right now the best I can do is a transmission gate DFF architecture. Two D latches with reset for the DFF and one D latch for the output latching to store the value. Total of 30 transistors per bit. I cannot use dynamic architectures because the counter needs to go for several milliseconds. To get this to fit in my application I really need to drive this number down to 15-20 transistors.



I’m starting to think this isn’t possible to implement with so few devices and I may have to revisit the overall architecture of the system to accommodate using less bits.


This snippet from online is essentially what I have for the DFF but I implement t-gates instead of pass gates.

 

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The simplest DFF you can make is a dynamic DFF.
These see use in RF CMOS prescalers and PLL prescaler
front ends where a full-on CMOS DFF can't self-toggle
(D=Qb) at the VCO output signal frequency. The dynamic
DFF has about half the devices of a classical tgate
(or all-NAND) architecture.

This is all fine for a simple ripple counter but adding any
feedback logic at all, will ruin the high speed proposition.
So you tend to see only a few stages of DDFF used,
sometimes with a "pulse swallower" attached so you can
get (say) a 4/5 divide-by option. After that regular CMOS
will (you hope) be able to hang with a quarter of max
incoming frequency.

US6737900B1 - Silicon-on-insulator dynamic d-type flip-flop (DFF) circuits - Google Patents

A novel dynamic DFF method and apparatus using CMOS is disclosed. The present invention does not use ratioed logic transistors in implementing a first stage of the DFF design. Thus, PMOS and NMOS transistors, used in the first stage of the DFF circuit, do not have severely disproportionate...
patents.google.com
 

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Thanks for the fast response! I tried this architecture and it didn’t work for me because the leakage at the charge storage nodes was too significant. For the MSB, I have to hold it for more than 30ms. I took a look at a bunch of other dynamic architectures, there is a great paper out there on the topic of “TSPC”. Unfortunately none of them worked.

The only exciting thing I saw out there was some obscure paper about an SRAM ripple counter but I wasn’t able to reproduce the results and when you think about it, there’s nothing stoping the signal from going all the way to the end of the counter since it’s not edge triggered. Also the fact that BL and BLb don’t toggle is a head scratcher to say the least.




Well in any case, I think for my application it’s back to the drawing board because something small enough just doesn’t exist. Thanks again!
 

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The divide-clock-by-2 function can be performed by a memory cell made from two invert-gates, with the addition of hysteresis.

It changes state every other clock cycle, thanks to a capacitor arranged as a charge bucket. Values are carefully adjusted to rise above and below the logic gate's threshold of operation over a period of 2 clock cycles.

Instead of using logic gates, it should be possible to substitute a classic RS flip-flop made from 2 transistors. It's more or less the same as a static ram cell.

 

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Yeah, at 30ms you are in static 'flop territory.

Unless you're going to deploy a whole lot of counters I doubt
that spending a lot of time / thought on layout area is a waste
of both - certainly in really low-L nodes. Might step back and
ask chip I/Os what the die area will be, and figure how much
to care about shaving transistor count.
 
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