HELP. Design a High Voltage OpAmp

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vadim888

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Hi All,

I have a student project "Design a high-voltage CMOS OpAmp",

and I have two questions:

Wich architecture is better for high voltage OpAmp (Voltage range 50-110 V) and why?


If you have a papers or books related to my topic, please give a link.

Thanks in advance,
Vadim
 

I would be looking at folded cascode and using HV devices
(like LDMOS) in the diff pair and the cascode guards. That
will let you "pin" most of the critical voltages that have to
slide across supply-driven and common-mode-driven ranges.
But you need to be wary of input differential voltage max
specs (which might force you to use thick gate MOS devices
with all of the performance and reliability (mV Vio drift)
negatives that go with them. Of course there's "thick" and
there's "thick" - >1000A on 40V range MOSFETs while a
40V asymmetric LDMOS can be had from a 5V, ~100A gate
ox - are you riding a pony, or an ox?
 
Thank you for your answer.


I didn't really get what do you mean in last sentence

" are you riding a pony, or an ox? "

Which layer I'm using for connections? or what.
 

I mean, are you using a flow that only has thick gate plain
MOS (ox), or are you using drain-extended / LDMOS with a
thinner gate ox (pony)? Each has their uses, and demands.
 

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