umairsiddiqui
Full Member level 2
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i'm assigned debugging gatelevel verilog code of 64-bit parititioned ALU design.
its my first research-based vlsi job and i'm assigned such a task...............
any way, its my first gatelevel debugging...any code hacking and simulation tips
& tricks, papers related to this issue. also suggest papers/books on general
datapath design.................................................................
its my first research-based vlsi job and i'm assigned such a task...............
any way, its my first gatelevel debugging...any code hacking and simulation tips
& tricks, papers related to this issue. also suggest papers/books on general
datapath design.................................................................