btismylove
Newbie level 1
I writed a verilog-a code in cadence is show below,
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`include "constants.vams"
`include "disciplines.vams"
module DAC_va(in, out);
parameter real fullscale = 5;
parameter integer maxbit = 10;
parameter integer bit = 10;
input [0:bit-1] in;
output out;
electrical out;
electrical [0:bit-1] in;
real vlump[maxbit:1];
real vout[maxbit:1];
real outv, vth;
integer i;
integer code[bit-1:0];
analog begin
@(initial_step) begin
vth = fullscale / 2;
for (i = 1; i <= maxbit; i = i + 1) begin
vlump = fullscale / pow(2, i);
end
end
end
endmodule
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but, spectreHDL compiler of cadence is return error message is
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Error found by spectre during SpectreHDL compile.
"/user1/chienju/opus/veriloga/DAC_va/veriloga/veriloga.va", line 6: Error:
mismatch in size of formal and actual for `in'.
Exiting SpectreHDL compilation.
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Who can help me, thanks.
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`include "constants.vams"
`include "disciplines.vams"
module DAC_va(in, out);
parameter real fullscale = 5;
parameter integer maxbit = 10;
parameter integer bit = 10;
input [0:bit-1] in;
output out;
electrical out;
electrical [0:bit-1] in;
real vlump[maxbit:1];
real vout[maxbit:1];
real outv, vth;
integer i;
integer code[bit-1:0];
analog begin
@(initial_step) begin
vth = fullscale / 2;
for (i = 1; i <= maxbit; i = i + 1) begin
vlump = fullscale / pow(2, i);
end
end
end
endmodule
-----------------------------------------------------------
but, spectreHDL compiler of cadence is return error message is
-----------------------------------------------------------
Error found by spectre during SpectreHDL compile.
"/user1/chienju/opus/veriloga/DAC_va/veriloga/veriloga.va", line 6: Error:
mismatch in size of formal and actual for `in'.
Exiting SpectreHDL compilation.
-----------------------------------------------------------
Who can help me, thanks.