shuchong
Newbie level 2
The functional simulation is OK, but ERROR info appeared during back-end simulating, such as:
Time: 13043 ps Iteration: 0 Instance: /vfifft_tf/UUT/\mifft/irom3/B5\
# ** Error: d:/Xilinx/verilog/src/simprims/X_RAMB16_S18.v(507): $setup( negedge ADDR[9] &&& EN:12932 ps, posedge CLK:13043 ps, 350 ps );
# Time: 13043 ps Iteration: 0 Instance: /vfifft_tf/UUT/\mfft/rom1/B5\
# 100.0ns 0
# ** Error: d:/Xilinx/verilog/src/simprims/X_FF.v(40): $hold( posedge CLK:113002 ps, negedge I &&& (in_clk_enable == 1):113246 ps, 381 ps );
How to cope with it?
Time: 13043 ps Iteration: 0 Instance: /vfifft_tf/UUT/\mifft/irom3/B5\
# ** Error: d:/Xilinx/verilog/src/simprims/X_RAMB16_S18.v(507): $setup( negedge ADDR[9] &&& EN:12932 ps, posedge CLK:13043 ps, 350 ps );
# Time: 13043 ps Iteration: 0 Instance: /vfifft_tf/UUT/\mfft/rom1/B5\
# 100.0ns 0
# ** Error: d:/Xilinx/verilog/src/simprims/X_FF.v(40): $hold( posedge CLK:113002 ps, negedge I &&& (in_clk_enable == 1):113246 ps, 381 ps );
How to cope with it?