HELP:back-end simulation ERROR

[shuchong]

The functional simulation is OK, but ERROR info appeared during back-end simulating, such as:
Time: 13043 ps Iteration: 0 Instance: /vfifft_tf/UUT/\mifft/irom3/B5\
# ** Error: d:/Xilinx/verilog/src/simprims/X_RAMB16_S18.v(507): $setup( negedge ADDR[9] &&& EN:12932 ps, posedge CLK:13043 ps, 350 ps );
# Time: 13043 ps Iteration: 0 Instance: /vfifft_tf/UUT/\mfft/rom1/B5\
# 100.0ns 0
# ** Error: d:/Xilinx/verilog/src/simprims/X_FF.v(40): $hold( posedge CLK:113002 ps, negedge I &&& (in_clk_enable == 1):113246 ps, 381 ps );

How to cope with it?

 

[xirix]

It seems your design doesn't met the setup/hold requirements for related parts. Try another constraints set for synthesis or insert some buffers to avoid setup/hold errors.

 

[maestor]

I agree with xirix,

The setup time for your BlockRAM in input ADDR[9] &&& EN is not met.
And the hold time in your FF somewhere...

How to cope with it...? not sure man (sounds very design specific to me :roll: ), it sounds to me as problem in your Verilog. You could change your timing constraints in your Synthesis tool as a first step. If still doesn't work try recoding those particular signals, adding some pipelining might help.

-maestor