fifo design
this can be done with two schemes,
A-adding an extra bit on the counter used as a flag, for example if you have a 16 word FIFO, then you use a 5 bit counter rather than 4-bit counter, this way comparing this extra bit will flag you if you are going to full or empty.
B-to use a direction flag according to the position of the counter in a four quadrant, i.e. according to the last two bits of the counter if the read lags the write then this flag may be used to indicate that you are going to be empty and if the write lags the read then you r going to be full, this direction flag simply informs when an equality condition happens wether if you are full or empty.
you can use an asynchronous set/reset FF to do this flag, however if you want to stick with the reuse methodology manual rules you can use a flancter.
The second technique is more appealing to me rather in high speed FIFO.
Note that FIFO design includes other technical issues you have to take care of, llike metastability and glitches occurs during comparison of counters.
metastability can be solved using the ordinary two cascaded FF metastability filters
glitches can be solved using gray code counter, and with low delay on nets you can improve the uncertainity time in your design, if you used a gray code counter you will not have to worry about glitches "non will occur".
gray counter can be done using a binary counter followed by binary-to-gray conversion and registeration, the binary counter can address the FIFO while the encoded gray code can be used for comparison this technique will decrease you fanout but increase the area, suitable for high speed application.