if (!pre_ld_Frame_out)
A=17'bz_zzzz_zzzz_zzzz_zzzz;
else
begin
A=address;
#7 DOUT=1'b1;
#45 A=17'bz_zzzz_zzzz_zzzz_zzzz;
DOUT=1'b0;
end
end
echo47 said:. You need to find some other way (maybe a shift register or possibly a DLL) to generate the delay you want.
Can you give me some examples ?The typical way to read from static SRAM is to output the address and control signals on one clock, and then latch the read data on a later clock (after tAA). If you really need to float the address bus, then you can do so at the same time you latch the read data. But normally the only signal that needs to be floated is the data bus, so you can switch from writing to reading
I found this in another Post (clock problem),I want to use this module and do some Simulation but same thing happen to me ,this module in" Simulate Behavioral Model" is ok ,but in"Simulate Post-Translate verilog Model" is lost wave clkout=Stxmodule top (clk, clkout);
parameter divider = 25000000 / 400; // must be an even number
input clk;
reg [15:0] count = 0;
output reg clkout = 0;
always @ (posedge clk) begin
count <= count == (divider / 2 - 1) ? 0 : count+1;
clkout <= clkout + (count == 0);
end
endmodule
module top (clk, count, clkout);
parameter divider = 25000000 / 400; // must be an even number
input clk;
output reg [15:0] count = 0;
output reg clkout = 0;
always @ (posedge clk) begin
count <= count == (divider / 2 - 1) ? 0 : count+1;
clkout <= clkout + (count == 0);
end
endmodule
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