Help about Sigma Delta modulator

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RDRyan

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How to implement a sigma delta modulator in verilog?
I want to use a MASH1-1-1 simga delta modulator in fractional-N PLL. how to implement it in actual circuit? Can anyone give some suggestion or some references?

thanks very much!

Ryan
 

To build a verilig model, you have 2 ways (those are the ones I know) :

1-A simplified way :You can use the laplace_nd({num coeffs},{denom coeffs})
to implement the NTF of the DS modulator (note that this is valid only for VerilogA or VerilogAMS).

2-Build a behavioral model for each accumulator ,register ,adder ,subractor...etc.
Then connect them (for example in a schematic) and simulate the new block .
I've tried the second way (but I used VHDL) and it gave good results .
 

    RDRyan

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I have made a behavioral model. But it is too difficult
to implement the noise cancellation network in MASH 1-1-1.

Thank you very much! I will try again.
 

I have implemented an order 2 and order3 sigma delta modulator on FPGA (verilog).But many papers say that high order sigma delta modulator will be better.I just wonder if someone has implemented high order sigma delta modulator.I used some coefficients of some paper from IEEE,they can not work.
 

I used VHDL to implement a 3rd order sigma delta modulator (single loop architecture). please can you give me an example of vhdl code because i'am a beginig in vhdl modelling.

thanks very much!
Noura
 

Check out the paper:
CMOS Delta-Sigma Frequency Synthesizer with a New Frequency Divider and a Simplified MASH Structure.

Soo-Hwan Kim, Min-Sun Keel, Ki-Won Lee and Suk-Ki Kim
 

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