help about "SDFA Error: Failed to find HOLD timingcheck

[Rachel]

failed to find hold timingcheck

gate level sim in Verilog XL with sdf file generated by synopsys , error occurs at "(HOLD (COND RN == 1 (posedge D)) (COND RN == 1 (negedge CKN)) (0.052:0.055:0.055))" in sdf, but ok when change the sdf file to "(HOLD (posedge D) (negedge CKN) (0.052:0.055:0.055))" , why ?
Can I generate a sdf without "COND" keywords ? Or should I change the sim library which describe the D Flip-Flop with asynchronous reset as " $hold ( negedge CKN, posedge D &&& _docheck1, 100000.0:100000.0:100000.0
, notifier );" ?

 

[cdic]

a error: failed to find hold timingcheck

check sdf version when you output it from Design Compiler

 

[Rachel]

hold timingcheck

It's sdf 2.1 . If I use "write_sdf -veriosn 1.0" , no "COND" keyword in sdf file. Verilog-XL don't support sdf 2.1 ? And NC ?

 

[kfy]

verilogxl+sdf

Normally , the sdf version is v2.1.
In your case , you shold to check the SDPD ( state depend path delay)whether are the same between Verilog and Synopsys or not .

 

[roli]

sdf cond

See Topic :

**broken link removed**

It is very close problem resolution. It uses 2 options to solve the incompatibilities problems between DC SDF output and Verilog:
1. A Perl script to fix, or
2. Feeding PrimeTime with your DC generated SDF & Netlist, having PrimeTime producing a new SDF output, which is now compatible with Verilog.

Hope this helps....