library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity shif1_array is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
x : out STD_LOGIC_VECTOR(15 downto 0));
end shif1_array;
architecture Behavioral of shif1_array is
signal msg_array: STD_LOGIC_VECTOR(0 to 63);
constant PHONE_NUMBER: STD_LOGIC_VECTOR(63 downto 0) :=x"248D656D1490FFFF";
begin
process(clr,clk)
begin
if clr='1' then
msg_array <= PHONE_NUMBER;
elsif (clk'event and clk ='1')then
msg_array (0 to 59)<= msg_array (4 to 63);
msg_array (60 to 63)<= msg_array (0 to 3);
end if;
end process;
x <= msg_array (0 to 15);
end Behavioral;