wdd
Member level 3
hi all,
In my design, the TSMC CM025 process is used.
GBW need to be higher than 500MHz, so the gm of input NMOS is fixed to 2*phi*Cl*700MHz(Cl is the load capacitance, which is 3pF).
AC and PAC simulation shows the GBW is 220MHz(phase margin is 85), much less than 700MHz,then I checked the nondominant pole(located larger than 4.5GHz, is enough i think). When the cursor is moved to phase margin= 70 point ,the frequency is about 900MHz.
So how can I modify the circuit to increase the GBW (also reduce the phase margin to about 70)? The topology is telescopic OTA with NMOS transisitor as input, the OTA is used in pipelined ADC.
Thanks a lot!!
wdd
In my design, the TSMC CM025 process is used.
GBW need to be higher than 500MHz, so the gm of input NMOS is fixed to 2*phi*Cl*700MHz(Cl is the load capacitance, which is 3pF).
AC and PAC simulation shows the GBW is 220MHz(phase margin is 85), much less than 700MHz,then I checked the nondominant pole(located larger than 4.5GHz, is enough i think). When the cursor is moved to phase margin= 70 point ,the frequency is about 900MHz.
So how can I modify the circuit to increase the GBW (also reduce the phase margin to about 70)? The topology is telescopic OTA with NMOS transisitor as input, the OTA is used in pipelined ADC.
Thanks a lot!!
wdd