Hi Hurricane,
If you build a ripple counter (asynchronous), then when the input changes to increase the count, the counter registers will go through a sequence of changes, with each register clocking the next one, until the final result is obtained.
Each of these intermediate register changes lasts for a finite time - if you use the output, you will see values that are not 'correct' until all the registers have finished toggling.
That is where a synchronous counter is useful - all the registers change state together to give a final value - there are no intermediate values.
Whether you need a clock (or synchronous counter) depends on what you are doing with the counter output. If you are driving just an LED display for instance, the brief intermediate results do not matter. If you are using the counter to divide a signal and compare it, to produce another output that could be considered a clock, then you must use a synchronous counter. Also, if you are reading the counter with a microcontroller or similar, you might read the intermediate values unless you have a 'count ready' signal, or clock.
Does this help? If not, please give some more detail of what you are trying to do.
I am learning CPLD's and have just designed from logic gates (not in HDL) a frequency/period counter that uses four 32-bit counters - one synchronous to divide a clock into multiple slower clocks, and three asynchronous with 'count finished' signals to the MCU.
Cheers,
FoxyRick.