help about 50ns filter of I2C

[sadfish]

i2c filter

Is there anybody know how to design the 50ns filter for I2C?
It is used to filter the spikes of input signal.
is it a RC filter? can anybody give me a schemactic?

 

[rajesh13]

i2c spike filter

Is there anybody know how to design the 50ns filter for I2C?
It is used to filter the spikes of input signal.
is it a RC filter? can anybody give me a schemactic?

Is it related to 50ns Spike suppression. What I understood from the I2C pad is that it should reject a glitch or pulse less then 50ns.

When I designed a I2C pad in 0.13u Technology. I used RC filter. I will suggect that you too go for RC as it simple to realize.

 

[rfdipper]

i2c spike

have a question also...
some applications uses schottky diodes connected to supply voltage and ground. Is this enough to suppress spikes or an additional RC filter needed? And since diodes have intrinsic capacitance when reversed bias, can we just use them?

 

[rajesh13]

i2c spike suppression

have a question also...
some applications uses schottky diodes connected to supply voltage and ground. Is this enough to suppress spikes or an additional RC filter needed? And since diodes have intrinsic capacitance when reversed bias, can we just use them?

I am not sure about this solution But in case of I2C pad, this pulse suppression of 50ns is in specification which you have to satisfy. I don't think any body will take chances.

 

[sadfish]

i2c pulse filter implementation

hi! thank your guys!
But can anybody give me schematic to refer?
what's bandwith of the filter?

 

[sadfish]

i2c pulse filter

what the 50ns means?
does it need to combined with the VHYS of the following schmitt trigger ?
Then the signals witch pulse width is smaller than 50ns can not pass the schmitt trigger.
If so, why can I not use a signal witch is the Xor of the input signal and 50ns delay input signal to control the input signal. it can also make the singal witch pulse width is smaller than 50ns can not pass.

 

[rajesh13]

i2c 50ns spike

I can tell you what I used in my circuit.
Basically I used one schmitt trigger, After that two capacitors (one to vdd & another to gnd). This will be equivalent to RC low pass, (R I am refering to that of the MOS). After that you can connect another schmitt trigger.

So its basically

signal-->schmitt trigger->CAP to vdd & gnd->2nd Schmitt trigger.

So to design,choose the capacitor & then size the First schmitt trigger mos's W/L so to suppress the 50ns Pulse.

This 50ns pulse suppression means that if I give 50ns Pulse (whose logic high time is 50ns) then it should not be reflected to the output to the core side.(Not even glitch).

But there is some ambiguity, The I2C specs does not specify whether it is single pulse or multiple stream of pulses. Beacause in the later case, after some time, the circuit will start responding to the stream of pulses as the internal points do not have time to discharge to steady state value.

 

[djalli]

i2c spike suppression filter

Why you dont built a switched delay filter to supress 50ns of signal? Is that what you want? Explain more please.

You can switch it using a SPST Single-Pole Signle-Throw.

 

[rajesh13]

i2c glitch

djalli,

are you saying to me. I just ported the design from 0.18u to 0.13u cmos technolgy. I found the method which I used to be much simpler & effective.

 

[sadfish]

i2c glitch filter

If you built a switch delay filter to suppress 50ns of signal, you need another clock signal. I agree with rajesh13, his resolution is simpler & effective.

 

[gururajb]

Re: i2c 50ns spike

Rajesh,

Could you please provide any documents for the design of glitch filter that explains the working of glitch filter.
How to choose the values of C and MOS (W/L) ?
What is the architecture of schmitt trigger to be used ?

Thanks and regards,
Gururaj B

I can tell you what I used in my circuit.
Basically I used one schmitt trigger, After that two capacitors (one to vdd & another to gnd). This will be equivalent to RC low pass, (R I am refering to that of the MOS). After that you can connect another schmitt trigger.

So its basically

signal-->schmitt trigger->CAP to vdd & gnd->2nd Schmitt trigger.

So to design,choose the capacitor & then size the First schmitt trigger mos's W/L so to suppress the 50ns Pulse.

This 50ns pulse suppression means that if I give 50ns Pulse (whose logic high time is 50ns) then it should not be reflected to the output to the core side.(Not even glitch).

But there is some ambiguity, The I2C specs does not specify whether it is single pulse or multiple stream of pulses. Beacause in the later case, after some time, the circuit will start responding to the stream of pulses as the internal points do not have time to discharge to steady state value.