pz5921087
Member level 1
As you can see the structure, it's a 8it SAR ADC, we just replace the capacitor array with split capacitor array to realize a 12bit 1K sampling rate SAR ADC. Its designed for EEG singal processing which has very low frequency.
Now we have builted an ideal model in cadence and use ideal DAC to convert the ADC output. We measured the THD by calculator that shows only -63dB. But it supposed to have a -74dB THD theoretically. Actually we also test the transient result and found that all the sample and hold values are correct and accurate. but why the THD is not sufficient? Is my measurment method of THD wrong? Can anybody explain? Thx!
This problem made me almost crazy.... The deadline for this project is approaching
Now we have builted an ideal model in cadence and use ideal DAC to convert the ADC output. We measured the THD by calculator that shows only -63dB. But it supposed to have a -74dB THD theoretically. Actually we also test the transient result and found that all the sample and hold values are correct and accurate. but why the THD is not sufficient? Is my measurment method of THD wrong? Can anybody explain? Thx!
This problem made me almost crazy.... The deadline for this project is approaching