help a noob - VHDL code

Code VHDL - [expand]
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Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
 
Entity ALU is
    Port ( A, B : in  STD_LOGIC_vector (3 downto 0);
           Sel : in  STD_LOGIC_vector (3 downto 0);
              Z: out STD_LOGIC_vector (3 downto 0));
              
              
                          
End ALU;
Architecture job of ALU is
signal Mid: STD_LOGIC_vector (3 downto 0);
 
 
Begin
Process (sel,A,B)
Begin 
        if (sel="000") then Mid <= A or B; 
        elsif (sel="001") then Mid <= A and B;
        elsif (sel="010") then Mid <= A nor B;
        elsif (sel="011") then Mid <= A nand B;
        elsif (sel="100") then Mid <= A xor B;
        elsif (sel="101") then Mid <= A nand B;
        elsif (sel="110") then Mid <= A xnor B;
        else Mid <= std_logic_vector(unsigned(A) + unsigned(B));        
        end if;
End process;
 
Process (sel,mid)
Begin
        if (sel="111") and (mid <"00101") then Z    <= "1000" ;
        elsif (sel="111") and (mid <"01001") then Z <= "0100" ;
        elsif (sel="111") and (mid <"01101") then Z <= "0010" ;
        elsif (sel="111") and (mid <"10001") then Z <= "0001" ;
        else Z <="0000";
        end if;
End process;  
End  job;