Hellp to GDM1602A LCD !

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Dinho

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Hello people,

I start short time to student VHDL, and in this moment I can not solve one problem.

I want use the LCD GDM1602A is in UP3 Education Kit the Altera.

But I don’t know how I can do this. My Idea is use one signal (b) for came the other code to show your velour in LCD display, and use other signal (flag_lcd) to inform when have to exchange information on the display.

If anyone can help me thank you people.

I did this code but it does not work.

-- FILE NAME : Liquid Crystal Display
-- AUTHOR : Dinho.
-- ---------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Libraries
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
ENTITY tela IS
generic(
COUNT_LENG : integer := 8
);
PORT(
LCD_RS ut std_logic:='0'; -- Resgister select (Seleciona registrar)
LCD_RW ut std_logic:='0'; -- Read / Wirte
LCD_E ut std_logic:='0'; -- Enable signal
clk :in std_logic; -- Clk kit
SF_D ut std_logic_vector(COUNT_LENG-1 downto 0):= (others => '0'); -- informacao frequencia (quero)
b :in std_logic_vector(4 downto 0):= (others => '0'); -- valor do divisor de clk
flag_lcd :in std_logic:='0' -- controla a escrita lcd
);
END tela;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE tela OF tela IS

-----------------------------------
-- Signal Declarations
-----------------------------------

type state_type is (stA, stB, stC, stD, stE);

signal state : state_type := stA;
signal clken : std_logic_vector(16 downto 0):= (others => '0');
signal reset : std_logic := '0';

signal enable : std_logic := '0';
signal counter : std_logic_vector(2 downto 0) := "000";

signal digit1 : std_logic_vector(7 downto 0):= (others => '0');
signal digit2 : std_logic_vector(7 downto 0):= (others => '0');

signal b01_sr : std_logic_vector(1 downto 0):= (others => '0'); --registrador de borda
signal clken_sr : std_logic_vector(1 downto 0):= (others => '0');

BEGIN
-----------------------------------
-- Asynchronous Assignments
-----------------------------------

digit2 <= "00110000" when b = "00000" else
"00110001" when b = "00001" else
"00110010" when b = "00010" else
"00110011" when b = "00011" else
"00110100" when b = "00100" else
"00110101" when b = "00101" else
"00110110" when b = "00110" else
"00110111" when b = "00111" else
"00111000" when b = "01000" else
"00111001" when b = "01001" else
"00110000" when b = "01010" else
"00110001" when b = "01011" else
"00110010" when b = "01100" else
"00110011" when b = "01101" else
"00110100" when b = "01110" else
"00110101" when b = "01111" else
"00110110" when b = "10000" else
"00110111" when b = "10001" else
"00111000" when b = "10010" else
"00111001" when b = "10011" else
"00111010";

digit1 <= "00110000" when b = "00000" else
"00110000" when b = "00001" else
"00110000" when b = "00010" else
"00110000" when b = "00011" else
"00110000" when b = "00100" else
"00110000" when b = "00101" else
"00110000" when b = "00110" else
"00110000" when b = "00111" else
"00110000" when b = "01000" else
"00110000" when b = "01001" else
"00110001" when b = "01010" else
"00110001" when b = "01011" else
"00110001" when b = "01100" else
"00110001" when b = "01101" else
"00110001" when b = "01110" else
"00110001" when b = "01111" else
"00110001" when b = "10000" else
"00110001" when b = "10001" else
"00110001" when b = "10010" else
"00110001" when b = "10011" else
"00111010";

SF_D <= "00000001" when counter = "000" else -- Clear
"00001000" when counter = "001" else -- Clear
"01000010" when counter = "010" else -- B
"00111101" when counter = "011" else -- =
digit1 when counter = "100" else -- Primeiro Digito
digit2; -- Segundo Digito


LCD_RS <= '0' when counter = "000" else
'0' when counter = "001" else
'1' when counter = "010" else
'1' when counter = "011" else
'1' when counter = "100" else
'1';

LCD_E <= enable;


-----------------------------------
-- Processes
-----------------------------------

PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk = '1')THEN -- edge of the clock
clken <= clken +1;

clken_sr <= clken_sr(0) & clken(16);

if clken_sr = "01" then

b01_sr <= b01_sr(0) & flag_lcd ;

-- ESTADO A
if state = stA then
if b01_sr = "01" then
enable <= '0';
counter <= "000";
state <= stB;
else
state <= stA;
end if;
end if;

-- ESTADO B
if state = stB then
enable <= '0';
state <= stC;
end if;

-- ESTADO C
if state = stC then
enable <= '1';
state <= stD;
end if;

-- ESTADO D
if state = stD then
enable <= '0';
state <= stE;
end if;

-- ESTADO E
if state = stE then
counter <= counter + '1';
if counter = "101" then
state <= stA;
else
state <= stB;
end if;
end if;

end if;

end if;
end process;
end tela;



Thank you very much.
Best regards,
 

Hi Dinho,

Did you make the simulation? If so you can compare your simulation with the timing diagram in the datasheet (GDM1602A), this way you may see what is wrong with your code.

Alex
 

Alex02 said:
Hi Dinho,

Did you make the simulation? If so you can compare your simulation with the timing diagram in the datasheet (GDM1602A), this way you may see what is wrong with your code.

Alex
Click to expand...

Hi Alex,
I did the simulation , but I don’t have know how I do change my code to comply with the rules of the display. I put in annex the rules of LCD (GDM1602A), my simulation and LCD Instruction Table. In the manual the UP3 Education Kit the Altera have this instruction for initialization LCD, but I do not know the meaning for example in POWER ON instruction says I have to write 0 0 0 0 0 0 1 D C B , what significance the letters D, C and B ?

LCD Initialization:

Normally LCD itself executies internal reset operations at the power up. But if the power suplly condition is not satisfied the internal reset circuit would not operate properly. It is better to initialization sequence by instruction.

Initializing by instruction:

POWER ON - 15msec Delay – Function Set – 4.1msec Delay – Function set – 100microsec – Function Set – 5msec Delay – Function Set – Display OFF – Display ON – Entry Mode set.
LCD on UP3 board is of N = 1 (1/16 Duty) and F = 0 (5X7 dots ). After this sequence LCD is ready for operation.


annex:




Thank you very much.
Best regards.

---------- Post added at 19:43 ---------- Previous post was at 19:35 ----------

I forgot,

My clk master is 14.318MHz.

Thank you very much.
Best regards.
 

Dinho said:
...I have to write 0 0 0 0 0 0 1 D C B , what significance the letters D, C and B ?...
Click to expand...

Dinho

Is that what are you looking for ?


+++
 

Dinho,

You can do the initialization with andre_teprom's info, so you can also see the signals with the oscilloscope on the board.

BTW your simulation seems to be ok.

Alex
 

Hello people,

Yes andre_teprom, thanks.

I will do the initialization’s LCD, tonight I will change the code and tomorrow I try test in the KIT. I will make test with the oscilloscope too.

I will post tonight news about my code.

Thank you very much.
Best regards.
 

Hello people,
I change my code, I expect test in class today this code:

-- FILE NAME : Liquid Crystal Display
-- AUTHOR : Dinho

-------------------------------------------------------------------------------
-- Libraries
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
ENTITY tela IS
generic(
COUNT_LENG : integer := 8
);
PORT(
LCD_RS ut std_logic:='0'; -- Resgister select (Seleciona registrar)
LCD_RW ut std_logic:='0'; -- Read / Wirte
LCD_E ut std_logic:='0'; -- Enable signal
clk :in std_logic; -- Clk kit
SF_D ut std_logic_vector(COUNT_LENG-1 downto 0):= (others => '0'); -- informacao frequencia (quero)
b :in std_logic_vector(4 downto 0):= (others => '0'); -- valor do divisor de clk
flag_lcd :in std_logic:='0' -- controla a escrita lcd
);
END tela;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE tela OF tela IS

-----------------------------------
-- Signal Declarations
-----------------------------------

type state_type is ( st0, stA, stB, stC, stD, stE, st1_in, st2_in, st3_in, st4_in, st5_in, st6_in );

signal state : state_type := st0;
signal clken : std_logic_vector(18 downto 0):= (others => '0');
signal reset : std_logic := '0';

signal enable : std_logic := '0';
signal counter : std_logic_vector(2 downto 0) := "000";

signal digit1 : std_logic_vector(7 downto 0):= (others => '0');
signal digit2 : std_logic_vector(7 downto 0):= (others => '0');

signal b01_sr : std_logic_vector(1 downto 0):= (others => '0'); --registrador de borda
signal clken_sr : std_logic_vector(1 downto 0):= (others => '0');

signal clken_in : std_logic_vector(1 downto 0):= (others => '0'); -- clk Initializing
signal ini : std_logic_vector(3 downto 0) := "1111"; -- Initializing by instruction

BEGIN
-----------------------------------
-- Asynchronous Assignments
-----------------------------------

digit2 <= "00110000" when b = "00000" else
"00110001" when b = "00001" else
"00110010" when b = "00010" else
"00110011" when b = "00011" else
"00110100" when b = "00100" else
"00110101" when b = "00101" else
"00110110" when b = "00110" else
"00110111" when b = "00111" else
"00111000" when b = "01000" else
"00111001" when b = "01001" else
"00110000" when b = "01010" else
"00110001" when b = "01011" else
"00110010" when b = "01100" else
"00110011" when b = "01101" else
"00110100" when b = "01110" else
"00110101" when b = "01111" else
"00110110" when b = "10000" else
"00110111" when b = "10001" else
"00111000" when b = "10010" else
"00111001" when b = "10011" else
"00111010";

digit1 <= "00110000" when b = "00000" else
"00110000" when b = "00001" else
"00110000" when b = "00010" else
"00110000" when b = "00011" else
"00110000" when b = "00100" else
"00110000" when b = "00101" else
"00110000" when b = "00110" else
"00110000" when b = "00111" else
"00110000" when b = "01000" else
"00110000" when b = "01001" else
"00110001" when b = "01010" else
"00110001" when b = "01011" else
"00110001" when b = "01100" else
"00110001" when b = "01101" else
"00110001" when b = "01110" else
"00110001" when b = "01111" else
"00110001" when b = "10000" else
"00110001" when b = "10001" else
"00110001" when b = "10010" else
"00110001" when b = "10011" else
"00111010";

SF_D <= "00001100" when ini = "0001" else -- POWER ON
"00110000" when ini = "0010" else -- data length (DL:8-Bit/4-bit)
"00101000" when ini = "0011" else -- numbers of display Line (N: =2-line/1-line)
"00100000" when ini = "0100" else -- Display font type (F: 5x11/5x8)
"00001000" when ini = "0101" else -- POWER OFF
"00001100" when ini = "0110" else -- POWER ON
"00101000" when ini = "0111" else -- numbers of display Line (N: =2-line/1-line)
"00100000" when ini = "1000" else -- Display font type (F: 5x11/5x8)
"00000001" when counter = "000" else -- Clear
"01000010" when counter = "001" else -- B
"00111101" when counter = "010" else -- =
digit1 when counter = "011" else -- Primeiro Digito
digit2; -- Segundo Digito


LCD_RS <= '0' when ini = "0001" else
'0' when ini = "0010" else
'0' when ini = "0011" else
'0' when ini = "0100" else
'0' when ini = "0101" else
'0' when ini = "0110" else
'0' when ini = "0111" else
'0' when ini = "1000" else
'0' when counter = "000" else
'1' when counter = "001" else
'1' when counter = "010" else
'1' when counter = "011" else
'1';

LCD_E <= enable;


-----------------------------------
-- Processes
-----------------------------------

PROCESS(clk)

BEGIN
IF(clk'EVENT AND clk = '1')THEN -- edge of the clock
clken <= clken +1;

clken_sr <= clken_sr(0) & clken(16);
clken_in <= clken_in(0) & clken(18);

if clken_in = "01" then

if state = st0 then
state <= st1_in;
end if;
-- Estado Initializing 1
if state = st1_in then
enable <= '0';
ini <= "0000";
state <= st2_in;
end if;

-- Estado Initializing 2
if state = st2_in then
enable <= '0';
state <= st3_in;
end if;

-- Estado Initializing 4
if state = st3_in then
enable <= '1';
state <= st4_in;
end if;

-- Estado Initializing 5
if state = st4_in then
enable <= '0';
state <= st5_in;
end if;

-- Estado Initializing 6
if state = st4_in then
ini <= ini + '1';
if ini = "1000" then
state <= stA;
else
state <= st2_in;
end if;
end if;
end if;

if clken_sr = "01" then

b01_sr <= b01_sr(0) & flag_lcd;

-- ESTADO A

if state = stA then
if b01_sr = "01" then
enable <= '0';
counter <= "000";
state <= stB;
else
state <= stA;
end if;
end if;

-- ESTADO B
if state = stB then
enable <= '0';
state <= stC;
end if;

-- ESTADO C
if state = stC then
enable <= '1';
state <= stD;
end if;

-- ESTADO D
if state = stD then
enable <= '0';
state <= stE;
end if;

-- ESTADO E
if state = stE then
counter <= counter + '1';
if counter = "100" then
state <= stA;
else
state <= stB;
end if;
end if;
end if;
end if;
END PROCESS;
end tela;
My new simulation so be :



I tried respect the instruction about Initializing the LCD.

I need change something in code?

Thank you very much.
Best regards.
 

Good night People,

I just arrived home from college, I was testing using this code:


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-- FILE NAME    : Liquid Crystal Display
-- AUTHOR       : Dinho
-------------------------------------------------------------------------------
-- Libraries
-------------------------------------------------------------------------------
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- Entity
-------------------------------------------------------------------------------
ENTITY tela IS
generic(
    COUNT_LENG  : integer   := 8
);
PORT(
            LCD_RS      :out    std_logic:='0';                                             -- Resgister select (Seleciona registrar)
            LCD_RW      :out    std_logic:='0';                                             -- Read / Wirte
            LCD_E       :out    std_logic:='0';                                             -- Enable signal
            clk         :in     std_logic;                                                  -- Clk kit
            SF_D        :out    std_logic_vector(COUNT_LENG-1 downto 0):= (others => '0');  -- informacao frequencia (quero)
            b           :in     std_logic_vector(4 downto 0):= (others => '0');             -- valor do divisor de clk
            flag_lcd    :in     std_logic:='0'                                              -- controla a escrita lcd
);
END tela;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
ARCHITECTURE tela OF tela IS
 
    -----------------------------------
    -- Signal Declarations
    -----------------------------------
 
    type state_type is ( st0, stA, stB, stC, stD, stE, st1_in, st2_in, st3_in, st4_in, st5_in, st6_in );
 
    signal state        : state_type := st0;
    signal clken        : std_logic_vector(18 downto 0):= (others => '0');
    signal reset        : std_logic := '0';
 
    signal enable       : std_logic := '0';
    signal counter      : std_logic_vector(2 downto 0) := "000";
 
    signal digit1       : std_logic_vector(7 downto 0):= (others => '0');
    signal digit2       : std_logic_vector(7 downto 0):= (others => '0');
 
    signal b01_sr       : std_logic_vector(1 downto 0):= (others => '0');               --registrador de borda
    signal clken_sr     : std_logic_vector(1 downto 0):= (others => '0');
    signal start        : std_logic := '0';                                             --inicia escrita display
 
    signal clken_in     : std_logic_vector(1 downto 0):= (others => '0');               -- clk Initializing
    signal ini          : std_logic_vector(3 downto 0) := "1111";                       -- Initializing by instruction
 
BEGIN
    -----------------------------------
    -- Asynchronous Assignments
    -----------------------------------
 
    digit2  <= "00110000" when b = "00000" else
               "00110001" when b = "00001" else
               "00110010" when b = "00010" else
               "00110011" when b = "00011" else
               "00110100" when b = "00100" else
               "00110101" when b = "00101" else
               "00110110" when b = "00110" else
               "00110111" when b = "00111" else
               "00111000" when b = "01000" else
               "00111001" when b = "01001" else
               "00110000" when b = "01010" else
               "00110001" when b = "01011" else
               "00110010" when b = "01100" else
               "00110011" when b = "01101" else
               "00110100" when b = "01110" else
               "00110101" when b = "01111" else
               "00110110" when b = "10000" else
               "00110111" when b = "10001" else
               "00111000" when b = "10010" else
               "00111001" when b = "10011" else
               "00111010";
 
    digit1  <= "00110000" when b = "00000" else
               "00110000" when b = "00001" else
               "00110000" when b = "00010" else
               "00110000" when b = "00011" else
               "00110000" when b = "00100" else
               "00110000" when b = "00101" else
               "00110000" when b = "00110" else
               "00110000" when b = "00111" else
               "00110000" when b = "01000" else
               "00110000" when b = "01001" else
               "00110001" when b = "01010" else
               "00110001" when b = "01011" else
               "00110001" when b = "01100" else
               "00110001" when b = "01101" else
               "00110001" when b = "01110" else
               "00110001" when b = "01111" else
               "00110001" when b = "10000" else
               "00110001" when b = "10001" else
               "00110001" when b = "10010" else
               "00110001" when b = "10011" else
               "00111010";
 
    SF_D <= "00001100"  when ini = "0001" else      -- POWER ON
            "00110000"  when ini = "0010" else      -- data length (DL:8-Bit/4-bit)
            "00101000"  when ini = "0011" else      -- numbers of display Line (N: =2-line/1-line)
            "00100000"  when ini = "0100" else      -- Display font type (F: 5x11/5x8)
            "00001000"  when ini = "0101" else      -- POWER OFF
            "00001100"  when ini = "0110" else      -- POWER ON
            "00101000"  when ini = "0111" else      -- numbers of display Line (N: =2-line/1-line)
            "00100000"  when ini = "1000" else      -- Display font type (F: 5x11/5x8)
            "00000001"  when counter = "000" else   -- Clear
            "01000010"  when counter = "001" else   -- B
            "00111101"  when counter = "010" else   -- =
            digit1      when counter = "011" else   -- Primeiro Digito
            digit2;                                 -- Segundo Digito
 
 
    LCD_RS   <= '0' when ini = "0001" else
                '0' when ini = "0010" else
                '0' when ini = "0011" else
                '0' when ini = "0100" else
                '0' when ini = "0101" else
                '0' when ini = "0110" else
                '0' when ini = "0111" else
                '0' when ini = "1000" else
                '0' when counter = "000" else
                '1' when counter = "001" else
                '1' when counter = "010" else
                '1' when counter = "011" else
                '1';
 
    LCD_E <= enable;
 
 
    -----------------------------------
    -- Processes
    -----------------------------------
 
PROCESS(clk)
 
BEGIN
    IF(clk'EVENT AND clk = '1')THEN                                 -- edge of the clock
        clken <= clken +1;
 
        clken_sr    <= clken_sr(0) & clken(16);
        clken_in    <= clken_in(0) & clken(18);
 
        if clken_in = "01" then
 
            if state = st0 then
                    state <= st1_in;
            end if;
            -- Estado Initializing 1
            if state = st1_in then
                enable <= '0';
                ini <= "0000";
                state <= st2_in;
            end if;
 
            -- Estado Initializing 2
            if state = st2_in then
                enable <= '0';
                state <= st3_in;
            end if;
        
            -- Estado Initializing 4
            if state = st3_in then
                enable <= '1';
                state <= st4_in;
            end if;
        
            -- Estado Initializing 5
            if state = st4_in then
                enable <= '0';
                state <= st5_in;
            end if;
        
            -- Estado Initializing 6
            if state = st4_in then
                ini <= ini + '1';
                if ini = "1000" then
                    state <= stA;
                else
                    state <= st2_in;
                end if;
            end if;
        end if;
 
        if clken_sr = "01" then
 
            b01_sr  <= b01_sr(0) & flag_lcd;
 
            if b01_sr = "01" then
                start <= '1';
            end if;
 
            -- ESTADO A
 
                if state = stA then
                    if start = '1' then
                        enable <= '0';
                        start <= '0';
                        counter <= "000";
                        state <= stB;
 
                    else
                        state <= stA;
                    end if;
                end if;
 
                -- ESTADO B
                if state = stB then
                    enable <= '0';
                    state <= stC;
                end if;
 
                -- ESTADO C
                if state = stC then
                    enable <= '1';
                    state <= stD;
                end if;
 
                -- ESTADO D
                if state = stD then
                    enable <= '0';
                    state <= stE;
                end if;
 
                -- ESTADO E
                if state = stE then
                    counter <= counter + '1';
                    if counter = "100" then
                        state <= stA;
                    else
                        state <= stB;
                    end if;
                end if;
        end if;
    end if;
END PROCESS;
end tela;


When I putted the code in FPGA display of kit happened this:




Why appeared “C3” in display? And even though I pressed been the button to change the data in the display nothing happened. It appeared that the LCD display depends on where you looked was still black.

I didn’t understand why my code not working:-(, I make LCD startup, who the manual says and respect the write mode timing diagram to LCD, at least I think so.:-?
Alright I have not had time to make tests using o oscilloscope on the board, I cannot confirm that the board is 100%ok.

This is my test bench:



Is there anybody who has a VHDL code for this LCD to work or get to know what's wrong in my code?:?:?


Thank you very much.:grin:
Best regards.
 

hi Dinho

I must advice you that when we take a complete code into the project, there is a big possibility to don´t work straight away.
Despite you had simulated waveform behaviours, seems you did not really integrated that with an virtual LCD component.

Due LCD modules are reasonable complex systems, some little details may block the proper working.
For while, I can sugest - like I commonly perform - try others implementations and adjust it to your need.

See an example taken from this same forum ( there are others ) :

https://www.edaboard.com/threads/147798/

+++
 

Good morning andre_teprom,

I’m sorry to write so later but I was very busy. Man I will read this codes and make other tests during this week and the next , after this or during this process I post my news.

Thank you very much.:grin:
Best regards.
 

maybe you can refer to a website fpga4fun,there is a LCD project
 

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