VLSI (Very Large scale integration) implies the schematic is intended to be etched on the same substrate. Probably in large numbers if it's imitating a cortical network. Evidently it sends and receives signals from other sections (c, d, Vin, Vbias, Spike out, Post Synaptic Input etc.). Certain signals probably require careful adjustment in order to create desired current flows. I imagine it requires repeated adjustments.
Perhaps it can succeed since you mention using 32nm process. It will require an expert to tell whether the original schematic can work, and whether your own simulation can work. It appears to make use of current mirrors and long-tail pairs. It would help if functions could be distilled into a simpler flow of steps. An expert certainly can do that better than I can.