The standard cell height is normally set up based on number of metal tracks. For example, you could design a 10-track standard cell library, which means that the height is 10 M1 track high. M1 track is minimum M1 width+spacing. For example, if your minimum metal pitch is 120nm (60nm wide metal, with 60nm spacing), the 10 track height would obviously be 120*10=1200nm or 1.2um. Now assuming you route the VDD/GND lines on the top and bottom metal track, you have about 8 M1 tracks free to route your wires and make contact to the transistor (VDD, GND, INPUTS and OUTPUTS). With Technology scaling, ideally you would want to keep the number of tracks the same, but since the M1 pitch scales every generation, you'd get a reduction in the standard cell height and essentially scaling in area.
So assuming you know the M1 pitch for a certain technology node (90nm or 40nm), and if you decide what the no of track height you want your standard cell to be, you can determine the height of the cell and figure out what it'll look at scaled nodes.