HDLCompilers Verilog Error-Urgent

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uniquadrion

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Hello,
I have this error below and I cant identify why. Is it because it is in not Verilog format? If it is not, how can I convert it into verilog format with the same code? It is very urgent so if you help with this, I would be very happy. For some reason the code looks gray-ish and gives and error that I cant identify.



-Thanks
 

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By default, ports in verilog are wires. You cannot assign to wires in an always block. You have to define it as a reg.
Change it to "output reg ResultOut"
 
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It's probably an old version of ISE so always @* will have to be changed to the old style always block with the fullvsensitivity list e.g. always @(list-of-RHS-signals)
 

sharath666, nice catch, but have any idea why all the code after always @ is grayed out? I don't use ISE's editor so I've never run across that behavior or have a clue why it would do that.
 

Well, ISE is not my editor too. But I still use ISE sometimes to test/synthesize some random piece of code. But I don't observe this graying out of code.
Maybe uniquadrion can throw some light on that..
 

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