Hazard problem in digital logic circuit design

digital logic hazards

I'm have learned much in digital circuit, and I am facing with hazard problem in my design, but I don't have deep document about this field.
Are there anyone having documents related to Hazard problem in logic circuit design.
Please give me some advices or any links that I could solve my problems.
Thanks.

what is hazard in digital circuit

What on earth is a hazard problem?
Sounds bad!!!

hazards,digital logic

raticus wrote;

What on earth is a hazard problem?
Sounds bad!!!

Raticus;

The best way to explain a hazard is this way.

Hazards are created when using minimizing techniques like k-mapping.
Sometimes the minimizing is too good.
For example, If you get you k-map to 2 gates but there is no overlap on the k-map. A condition may cause a short duration pulse from one on/off state to the other.
Sometimes the hazard isn't critical but...! and I mean a big BUT - It can cause unexpected results. These results usually cause undesired outputs etc...

I think the best way to deal with hazards is in the initial design phase of the circuit (paper and pencil). As your minimizing your equations, you can see the hazards on the k-map, paper, etc...
Here you can see which hazards (if any) are critical and must be dealt with and which are not critical because it will happen in a "don't-care" state.

I hope this explaination helps out a little. I know there are members who has more knowledge there.

Hope this helps.
WA

Hi,
How are u observing this problem?
One way of minimizing this is by using redundancies.

BRM

heck this link, it is a good document about glitches and hazards in electronic circuits

**broken link removed**

it is really noisesome problems

Honey
any undesired signals can be described as noise but hazards mainly occure due to different pathes delays that causes the signals that had been changed in in time T0 reaches the target at diffirent times Tx

I do absolutely agree with Al Farouk. Worse case is in a state machine jumping in a state due to hazard condition. This may drive you to the wall in a complex design. Simulation is not that evident, and if you implement redundancies to work it out, you design and timing are not equivalent.. So it is a very sensitive part that are sometimes overlooked.