Have other Formal logic equivalent check tool can use?

[minglittleyen]

Hello~
Have any tool can check logic equivalent for RTL vs netlist or netlist to netlist ? But not Cadence-LEC or Synopsys-Formality or Siemens (Mentor)-Questa tool.

Thanks

 

[dpaul]

Are ASIC design engineers able to much outside of Cadence/Synopsys/Mentor tools use?

 

[ahsrabrifat]

There are a few open-source or lesser-known commercial tools for logic equivalence checking (LEC) beyond Cadence LEC, Synopsys Formality, or Siemens Questa. You can consider Yosys, Symbiyosys etc.