have Multiplier code but i am getting error stating - near "end" : expecting identier

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEE.NUMERIC_BIT.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Array_Multiplier is
    Port (A,B : in bit_vector(3 downto 0);
      P: out bit_vector(7 downto 0);
          Result_Low : out bit_vector (3 downto 0);
          Result_High : out bit_vector (3 downto 0);
end Array_Multiplier;
 
 
architecture behavioral of Array_multiplier is
 
signal C1, C2, C3: bit_vector (3 downto 0);
signal S1, S2, S3: bit_vector (3 downto 0);
signal XY0, XY1, XY2: bit_vector (3 downto 0);
 
Component FullAdder_1_bit is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Cin : in  STD_LOGIC;
           Sum : out  STD_LOGIC;
           Cout : out  STD_LOGIC);
end Component;
 
 
Component HalfAdder_1_bit is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Sum : out  STD_LOGIC;
           Cout : out  STD_LOGIC);
end Component;
 
 
Component AND_1_bit is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : out  STD_LOGIC);
end Component;
 
begin
 
AB0(0) <= A(0) and B(0); AB1(0) <= A(0) and B(1);
AB0(1) <= A(1) and B(0); AB1(1) <= A(1) and B(1);
AB0(2) <= A(2) and B(0); AB1(2) <= A(2) and B(1);
AB0(3) <= A(3) and B(0); AB1(3) <= A(3) and B(1);
 
AB2(0) <= A(0) and B(2); AB3(0) <= A(0) and B(3);
AB2(1) <= A(1) and B(2); AB3(1) <= A(1) and B(3);
AB2(2) <= A(2) and B(3); AB3(2) <= A(2) and B(3);
AB3(3) <= A(3) and B(3); AB3(3) <= A(3) and B(3);
 
FulLAdder_4_bit_0: FullAdder_4_bit port map (AB0(2), AB1(1), C1(0), C1(1), S1(1));
FullAdder_4_bit_1: FullAdder_4_bit port map (AB0(3), AB1(2), C1(1), C1(2), S1(2));
FullAdder_4_bit_2: FullAdder_4_bit port map (S1(2), AB2(1), C2(0), C2(1), S2(1));
FullAdder_4_bit_3: FullAdder_4_bit port map (S1(3), AB2(2), C2(1), C2(2), S2(2));
FullAdder_4_bit_4: FullAdder_4_bit port map (C1(3), AB2(3), C2(2), C2(3), S2(3));
FullAdder_4_bit_5: FullAdder_4_bit port map (S2(2), AB3(1), C3(0), C3(1), S3(1));
FullAdder_4_bit_6: FullAdder_4_bit port map (S2(3), AB3(2), C3(1), C3(2), S3(2));
FullAdder_4_bit_7: FullAdder_4_bit port map (C2(3), AB3(3), C3(2), C3(3), S3(3));
HallAdder_1_bit_0: HalfAdder_1_bit port map (AB0(1), AB1(0), C2(0), S1(0));
HallAdder_1_bit_1: HalfAdder_1_bit port map (AB1(3), C1(2), C1(3), S1(3));
HallAdder_1_bit_2: HalfAdder_1_bit port map (S1(1), XY2(0), C2(0), S2(0));
HallAdder_1_bit_3: HalfAdder_1_bit port map (S2(1), AB3(0), C3(0), S3(0));
 
P(0) <= AB0(0);
P(1) <= S1(0);
P(2) <= S2(0);
P(3) <= S3(0);
P(4) <= S3(1);
P(5) <= S3(2);
P(6) <= S3(3);
P(7) <= C3(3);
 
Result_Low(0) <= AB0(0);
Result_Low(1) <= S1(0);
Result_Low(2) <= S2(0);
Result_Low(3) <= S3(0);
Result_High(0) <= S3(1);
Result_High(1) <= S3(2);
Result_High(2) <= S3(3);
Result_High(3) <= C3(3);
 
 
END behavioral;