Has anybod used X!linx Ch!pScope?

[maestor]

Hi guys,

Has anybody used ChipScope and can give some tips/opinions about it? price, complexity, documentation...

Thx

-maestor

 

[Bartart]

Hi!

It is easy to work with, just go througt the xapp. It is usefull if you debug small designs and when you have a BRAM free resources.

You can dl it for free @ xilinx site. All the documentation you need is on the net.

Good luck, Bart

 

[zape]

ChipScope is quite useful when debugging your application or even for checking the board integrity. But if you have few resources of BRAM and BUFG then you will have troubles. At the end is logic that must be placed and routed. I had a bad experience working with a virtex-e with all bufg used (one more is needed/recommended for the JTAG clock) and a device occupation of 40% and I did not succed.

 

[Vonn]

1- Can any body explains in 1 , 2, 3 how to use chipscope to debug my design

2- In my dsign iam using spartan II 200K connected to XC18V02 now when Iam connecting my Jtag Parallel IV cable should I connect it to the Prom jtag port or to the spartan jtag port ?

 

[zcq]

Any good document for guiding using CHipscope? The user guide is too long...

Thanks,

 

[Git]

2- In my dsign iam using spartan II 200K connected to XC18V02 now when Iam connecting my Jtag Parallel IV cable should I connect it to the Prom jtag port or to the spartan jtag port ?

Those ports should be daisy chained together, not separate, shouldn't they?


Git

 

[Vonn]

Is that a must ??
I used seperate ports and iam using the port of PROM to download the bitstream to it ; then at power up the PROM configure the FPGA
Is there any problem in this design ? please confirm

 

[Git]

There's no problem with it as far as I know, but it's unusual - you are throwing away the chance to use jtag to examine your design at the cost of a wiring change.

 

[Vonn]

I don't get it .. what do you mean by

"you are throwing away the chance to use jtag to examine your design at the cost of a wiring change."

Do you mean that I can't use chip scope in this case ? or what ?

 

[Git]

I'm not sure because I don't know if you have left any access to the JTAG port on the FPGA. Without JTAG access to the FPGA you certainly can't use Chipscope.

https://www.xilinx.com/ise/verification/chipscope_pro_sw_cores_6_2i_ug029.pdf

If you HAVE got jtag fpga access then it suggests you have two JTAG connectors, one for programming the configuration PROM and another for fpga boudary scan. Seems odd to me because as you go through the design iteration process of program -> debug -> program -> debug -> final program, you will have to keep changing your jtag lead over from one connector to the other. The whole point of jtag having TDO and TDI is that you daisy chain all jtag ports together and your jtag software can then see all those device and allow you to choose the one you want to work on.

Git

 

[Vonn]

I understand that i should switch the cable between the jtag ports of the PROM / FPGA in case of Programming / Debugging because I used separate ports ...

Now in order to summerize the manual of the chip sope ; I have founded this pdf in berkeley :
w*w-inst.eecs.berkeley.edu/~cs150/ Documents/ChipScopeDemo.PDF
It's very useful demo

I have followed the instructions written in this pdf but I have a problem when Iam trying to inst. the components of ICON and ILA ; that it can't be synthized ; the ISE can't find it in any LIB ???
Generating a Black Box for component <icon>.
Generating a Black Box for component <ila>.

Although I have included
library UNISIM;
use UNISIM.VComponents.all;

can any body help 8O