Has any one used save/resotre to speed up the simulation?

[santhosh007]

verilog save restore

Hi,
Have any one is using save/resotre to speed up the simulation?.

 

[paulki]

Re: save/restore

Hi Santhosh,
Can you please elaborate how the save/restore will improve the simulation speed?

-Paul

 

[santhosh007]

save/restore

Hi Paul,
for example you have 10 testcases, all of which say 50 ns of simulation time is common(may be intialization..), instead of running all the testcases from 0 time. you run one testcase till 50ns and save the simulation. then you need restore the saved snapshot and run the remaining testcases from 50ns. this way you can save the simualtion time.

 

[sharanbr]

Re: save/restore

Save restore per-se does not speed up the simulation but is used to take a snapshot of a simulation data at a particular instance and then re-start it from there.

What could be the advantage of doing that: one useful advantage of this is that one can pass parameters to the simulation which are used as conditional code in the testbench. For example, to dump the waveform data. So yeah, with save/restart one has the luxury of running the simulation without waves (which is definitely faster) and restart the simulation from an intermediate state with waves only if there is a failure.

Added after 7 minutes:

Hi Paul,
for example you have 10 testcases, all of which say 50 ns of simulation time is common(may be intialization..), instead of running all the testcases from 0 time. you run one testcase till 50ns and save the simulation. then you need restore the saved snapshot and run the remaining testcases from 50ns. this way you can save the simualtion time.

In theory this really looks awesome but its not that simple (in my own experience) in practice. The method you have described above can be used only if the tests already are a part of the testbench. You cannot add new tests to existing suite and rerun from an intermediate state using save/restore method. If you have found a way to do this, I would be really curious to understand...

 

[paulki]

Re: save/restore

Hi Santhosh,
Very good explanation. There are couple of techniques used in SoC regressions.
1. Booting will be done and first testcase will be executed, after the first test finish the INITIAL STATE will be restored by function calls and second test would be executed. (INITIAL STATE here means before what was the STATE of that Particular IP, that will be restored, this is different than the normal RESET phase). This is successfully implemented in many companies.
Some secondary level test cases may affect the Boot Sequence itself, in these scenario, this technique is very much useful. Here the attention need to be given for the function calls for bringing-back of the initial states, otherwise there are chances of affecting some other IPs functionality.

2. Other is Save/Restore. Here Boot itself is a PHASE, then only Test Execution phase. This also a useful technique, but some of the Mobile Application testcases can affect Boot sequence/Interrupts (think such scenario comes in the 3rd Test case in a regression suite). So re-boot is required since time and disk space required more. Another problem we found with this method is "Tool Crashes" while saving the boot and starting test execution phase. (This is applicable with which tool and support provided by the EDA vendor)

Based on application we can choose which scenario is better/best.

-Paul

 

[santhosh007]

save/restore

Thanks Paul. i am trying this to implement in the verilog testbench env.

sharanbr, yes you are right. this can be used while running the final regression. usually the initialization and calibration cycles take an hour to complete after that only the real simualtion starts.. instead of spending the so much time each test case, you can skip those states running again and again.