Harmonic Oscillator with ideal Opamp models

IMHO, talking about semantics only, the circuit you showed are (ideal) oscillators. So much so an (ideal) inductor has 0-resistance, your circuit has an opamp with 0-delay.

So much so an (ideal) inductor has 0-resistance, your circuit has an opamp with 0-delay.

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Not in the same way, I think. The circuit won't work with a hypothetic infinite GBW opamp as long it's comitted to regular feedback operation. The circuit only "works" in a numerical solver.

FvM said:

.. loop phase has wrong polarity in AC simulation.

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Sorry, but your all talk is going out of my head. I may not be very good with all the analog component (sorry I did not use circuit) behavior.
But Both the example are not fake example but giving expected simulation results.
Example 1: unstable with gain 20dB (as u said). because of positive f/b, ( that it self gives 180 degree phase shift). Output voltage is ever increasing. Phase margin 0 degree.
Example 2: Try to determine poles and zero, Here again positive f/b dominates over negative f/b, gives unstable behavior.
They can't be told oscillator. Because Oscillator behavior are well established but uncontrolled positive f/b is not.

But Both the example are not fake example but giving expected simulation results.

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Which simulation results do you refer to? Your results seem to be different from the results LvW reported (and that are well reproducable unter the said conditions). Did you a perform a simulation at all? If so, using which tool?

I simulated (ac,dc,tran) with Cadence spectre. All the result I got as I expected.
My point is, we all are seeing these circuits are in positive f/b. ( Remember positive f/b are always used for Hysteresis).
Here for simulation if we use Ideal opamp, its output voltage is not controlled (no VDD/VSS) so it has infinite range.
With positive f/b, Out put voltage can reach both the limits.

In real opamp, output is limited by rail potential. And output voltages are well controlled. Where B positive f/b we can provide lower/upper limit for Hysteresis.

Hi varunkant2k, I have problems to understand the meaning of your contributions (maybe I am "guilty" because of limited knowledge of your language).

I simulated (ac,dc,tran) with Cadence spectre. All the result I got as I expected.

What did you expect in case of ideal opamp models (constant but finite gain) ?

My point is, we all are seeing these circuits are in positive f/b. ( Remember positive f/b are always used for Hysteresis).

Always? I think only in connection with amplifier time delay (which is not existent for the ideal opamp model)

Here for simulation if we use Ideal opamp, its output voltage is not controlled (no VDD/VSS) so it has infinite range.
With positive f/b, Output voltage can reach both the limits.

I don't understand at all; which limits? VDD, VSS?

Finally, from your contribution it is not clear to me if you confirm my observations (simulation results) or not.

This applies also to your first contribution. I really don't know what you are saying:

unstable with gain 20dB (as u said). because of positive f/b,

Unstable with gain?

Output voltage is ever increasing. Phase margin 0 degree.

Are you referring to ideal or real opamp models?

Example 2: Try to determine poles and zero, Here again positive f/b dominates over negative f/b, gives unstable behavior.
They can't be told oscillator.

Again: Ideal or real models? More than that, the term "unstable" is to unspecific. This can mean saturation or oscillation.
It would be fine if you could clarify some points.
Regards
LvW

Sorry for not being clear. I will take care when I will write. Thank you. Now For your points:

LvW said:

I simulated (ac,dc,tran) with Cadence spectre. All the result I got as I expected.

What did you expect in case of ideal opamp models (constant but finite gain) ?

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When I tell positive feedback, that means it will go for instability. (in real or ideal that does not change the meaning).
Now the result I can expect, ( you may take all my explanations for ideal op amp)
Example 1: If ideal opamp gain is very high, It will make both of its input terminal potential equal and hence out put will go to negative. I am expecting same result with real opamp ( but out put voltage may not go to rail voltage)( i understand rail voltages to VDD/VSS/-VDD). Both the cases we are getting 180 degree phase shift. PM is 0. System is unstable. (see why)( we should not see the instability only if it oscillates.) Note:We can oscillate it by using the method as in example 2.
Example 2: Without diode output voltage should increase the same as in Example 1. The system is again unstable. If you add diode ( the way they are connected in example2) it will oscillate across positive and negative forward voltage of diode.

LvW said:

unstable with gain 20dB (as u said). because of positive f/b,
Unstable with gain?
Output voltage is ever increasing. Phase margin 0 degree.

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circuit is unstable (with gain 20dB ). because of positive f/b,(bcs PM =0] [i understand positive feedback is having infinite gain]
So, for your understanding , please do not try interpreting each line individually. Please read complete post and try to simulate and then comment. Each circuit are derived from their ideal behavior only.
Please do not be guilty, as it feels lack of sincerity. Better you also write sensitively, so visitors to the link get something logically.

Hello varunkant2k, thanks for replying.
However, I must confess it is not yet clear to me. You are mixing within one sentence some observations with some explanations, which makes the real content not very clear to me. I do not want to discuss about "terminal potentials", "rail voltages", "180 degree phase shift", "PM=0", and other terms.
(What is the meaning of ... positive feedback is having infinite gain ??)
Since you have access to SPECTRE it is interesting to learn, if you can confirm the following results.
Thus, I kindly ask you to shortly respond to the 4 observations from my side as listed below.

To example 1:
(a) Finite inverting gain (20 dB) for opamp ideal (no frequency dependence, without internal delay);
(b) instabilty (saturation at VDD or VSS) for real opamp model.

To example 2:
(a) Oscillations with fixed amplitude for opamp ideal; diode action: gain increase for rising amplitudes.
(b) instability (saturation at VDD or VSS) for real opamp model.

Which points can be confirmed by you and which not?
Thank you.
LvW

Hello varunkant2k, although unlikely, it may be the case, that Cadence shows different results for the said circuits even with ideal OPs. Basic SPICE simulators like PSpice or LTSpice show the results LvW reported. The output voltage limitation of the ideal PSpice OP model isn't required however, in contrast, the circuit is immediately latching up, if the output voltage ever touches the limit. So you can use a simple voltage controlled voltage source E element instead as simple ideal OP model, as shown below.

My impression from your post is however, that you didn't actually simulate with the ideal OP model rather than concluding the expectable results, which may be completely wrong.

FvM said:

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the circuit is immediately latching up, if the output voltage ever touches the limit. So you can use a simple voltage controlled voltage source E element instead as simple ideal OP model, as shown below.

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Thanks FvM for the clarification.
I didn't want to complicate the discussion - and therefore, I didn't report the oscillator behaviour (example#2) without amplitude limiting diodes.
But now, after "latching-up" was mentioned, I will add some further aspects:

* The oscillator in my example#2 will have a constant amplitude only if the gain gets larger for rising amplitudes. This "pathological effect" can be verified easily by evaluating the diode action and its location across the grounded resistor.

*Without diodes: The oscillator amplitude is rising continuously until the limits are reached (if included in the ideal model). As a consequence the gain starts to fall causing a further increase of the amplitude. This results in the so called "latch-up" effect as mentioned by FvM: The output voltage remains constantly at this upper limit.
(To be clear: No amplitude clipping effect like in classical oscillators). This "latch-up" is discussed by several authors (and verified by non-linear analyses based on describing functions).

*For real opamp models (at least one pole) this "latch-up" occurs immediately (without any oscillations) due to an RHP pole that is not present for the simple ideal opamp model.

I just simulated with spectre and got exactly the same results as FvM, using Euler and Gear2only integration methods.

JoannesPaulus said:

I just simulated with spectre and got exactly the same results as FvM, using Euler and Gear2only integration methods.

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JohannesPaulus, thank you for this information.
LvW

---------- Post added at 18:54 ---------- Previous post was at 18:50 ----------

That means: Also SPECTRE is not able to decide if a feedback circuit based on an excessively simplified opamp model will have a stable bias point under real conditions.

I've debated this issue with some people in the past. the issue is that an ideal opamp is able to solve Vo = Av*Vi, and with the resistors and whatnot in place with no delays labeled there is nothing that actually causes the positive feedback to be unstable from a control-loop standpoint. any engineer would realize the issue.

and similar sim issues exist for a variety of "ideal" components. you have ideal inductors and ideal caps and ideal switchs that can be used to generate unrealistic behavior. From what I recall, some sims have issues if you just have an LC tank by itself. I forget if it was that case, or if you specify an initial condition for just the inductor/capacitor but not both. eg, Vc = 1V, but without specifying inductor current, the bias point might be calculated as 10E30 A.

(it is also fun to look at the opamp's input differential voltage, as well as the output, for 2 < Av <10.)

permute said:

I've debated this issue with some people in the past. the issue is that an ideal opamp is able to solve Vo = Av*Vi, and with the resistors and whatnot in place with no delays labeled there is nothing that actually causes the positive feedback to be unstable from a control-loop standpoint. any engineer would realize the issue.
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Yes, no doubt about it.

there is nothing that actually causes the positive feedback to be unstable from a control-loop standpoint

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Maybe I have a limited knowledge of control theory, but I can't follow this consideration. In my understanding, a control loop works in the way, that an existing non-zero error signal causes a change of the manipulated value that reduces the error signal, in other words involves a negative feedback. As an equivalent to the discussed amplifier, consider an ideal P controller. As far as I'm aware of, no one would expect stable behavior for a P controller with inverted gain.

As previously mentioned, the SPICE simulator can achieve a convergent solution, because it's not bound to the operation principle of a control loop.

As far as I have understood permute's response he was referring to the ideal case (without any delay) only.

Yes, that's clear. But he was referring to control theory. I doubt, that you'll find a control theory example where a system with positive feedback and no delay (P controller + P plant) is analyzed as stable. In my view, it's explicitely contradicting the control loop standpoint.

at the same time, positive feedback itself is not unstable. I'd hope you'd find no one who would say that positive feedback was unconditionally unstable. You should be able to construct physically realizable circuits with positive feedback that are stable. Essentially, every opamp circuit ever constructed meets this requirement. Of course the matter isn't important because there is a loop gain of less than one. aka "gain margin". Positive feedback can be applied to some circuits and can actually stablize some specific systems.

Another example is "conditional stability". Such systems have phase margin, but not gain margin. basically, the phase crosses 360 deg with gain > 1, but then the phase crossed back before the gain reaches 1. This system is both stable, and physically realizable. I used to have a link with a good description and example. It appears to be very difficult to find back on google/yahoo.

I fear, there's a misunderstanding. When I was talking about positive feedback related to the present circuit (Examples.Circuit 1 respectively post #29), I presumed positive amplifier gain and as a result positive loop gain.

Circuit1 shows positive, frequency independent loop gain > 1. Although it has pseudo stable simulation results it's not stable "from a control loop standpoint", I think.

but why? The point to "conditional stability" is that you can have a system that, over some bandwidth, has the same condition. positive feedback and gain > 1. Yet such circuits are not unstable until the gain is reduced. If a physically realizable system can have positive feedback with gain over some bandwidth, is it unreasonable to have a stable ideal system with positive feedback and gain over infinite bandwidth?