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[SOLVED] Harmonic balance failed to converge of DC-DC converter

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Hi All,

I was working on a switched-capacitor DC-DC converter and I want to run harmonic balance to measure PSRR of the converter. However, the harmonic balance won't converge. I tried to increase the tstab, maxharm and oversample and non of that worked.
Could anyone give me some advices?
Thanks

Spectre log is in the attachment.
Here is my netlist:

Code: 
// Library name: Ideal_Components
// Cell name: Wire_Bonding_Model
// View name: schematic
subckt Wire_Bonding_Model GND VDD pad pcb
parameters C_pcb C_wire ind
    C20 (pcb GND) capacitor c=C_pcb
    C19 (pad GND) capacitor c=C_wire
    L0 (pad pcb) inductor l=ind
ends Wire_Bonding_Model
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: converter_core
// View name: schematic
subckt converter_core SW1 SW2 VSS Vcfly1 Vcfly2 Vin Vout
    M12 (Vcfly2 SW1 VSS VSS) nch_25_mac l=10u w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M9 (Vcfly2 SW2 VSS VSS) nch_25_mac l=400n w=10u multi=1 nf=1 sigma=1 \
        sd=310.0n ad=2.3e-12 as=2.3e-12 pd=20.46u ps=20.46u nrd=0.0155 \
        nrs=0.0155 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M11 (Vcfly1 SW1 Vout Vout) nch_25_mac l=10u w=400n multi=1 nf=1 \
        sigma=1 sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u \
        nrd=0.3875 nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 \
        mismatchflag=1
    M8 (Vcfly1 SW2 Vout Vout) nch_25_mac l=400n w=10u multi=1 nf=1 sigma=1 \
        sd=310.0n ad=2.3e-12 as=2.3e-12 pd=20.46u ps=20.46u nrd=0.0155 \
        nrs=0.0155 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M15 (Vcfly1 SW1 Vin Vin) pch_25_mac l=400n w=30u multi=1 nf=1 sigma=1 \
        sd=310.0n ad=6.9e-12 as=6.9e-12 pd=60.46u ps=60.46u nrd=0.00516667 \
        nrs=0.00516667 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 \
        mismatchflag=1
    M14 (Vcfly2 SW2 Vout Vout) pch_25_mac l=30u w=400n multi=1 nf=1 \
        sigma=1 sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u \
        nrd=0.3875 nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 \
        mismatchflag=1
    M13 (Vcfly2 SW1 Vout Vout) pch_25_mac l=400n w=30u multi=1 nf=1 \
        sigma=1 sd=310.0n ad=6.9e-12 as=6.9e-12 pd=60.46u ps=60.46u \
        nrd=0.00516667 nrs=0.00516667 sa=230.0n sb=230.0n sca=0 scb=0 \
        scc=0 mismatchflag=1
    M10 (Vcfly1 SW2 Vin Vin) pch_25_mac l=30u w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
ends converter_core
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: inverter_3
// View name: schematic
subckt inverter_3 VDD VSS Vin Vo
    M2 (Vo Vin VSS VSS) nch_25_mac l=280.0n w=1.2u multi=1 nf=3 sigma=1 \
        sd=310.0n ad=2.16e-13 as=2.16e-13 pd=2.68u ps=2.68u nrd=0.129167 \
        nrs=0.129167 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M1 (Vo Vin VDD VDD) pch_25_mac l=280.0n w=2.4u multi=1 nf=3 sigma=1 \
        sd=310.0n ad=4.32e-13 as=4.32e-13 pd=4.28u ps=4.28u nrd=0.0645833 \
        nrs=0.0645833 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
ends inverter_3
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: inverter_2
// View name: schematic
subckt inverter_2 VDD VSS Vin Vo
    M5 (net13 Vin VDD VDD) pch_25_mac l=400n w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M6 (Vo Vin net13 VDD) pch_25_mac l=400n w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M0 (Vo Vin net14 VSS) nch_25_mac l=400n w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M7 (net14 Vin VSS VSS) nch_25_mac l=400n w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
ends inverter_2
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: nor_1
// View name: schematic
subckt nor_1 A B VDD VSS Y
    M2 (net22 A VDD VDD) pch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 \
        sd=310n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
    M3 (Y B net22 VDD) pch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 \
        sd=310n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
    M4 (Y B net23 VSS) nch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 \
        sd=310n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
    M0 (Y A net24 VSS) nch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 \
        sd=310n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
    M5 (net23 B VSS VSS) nch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 \
        sd=310n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
    M6 (net24 A VSS VSS) nch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 \
        sd=310n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
ends nor_1
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: non_overlap_gen
// View name: schematic
subckt non_overlap_gen CLK SW1 SW2 VDD VSS
    I86 (VDD VSS net2 SW1) inverter_3
    I87 (VDD VSS net10 net23) inverter_3
    I60 (VDD VSS SW1 net25) inverter_3
    I61 (VDD VSS net23 SW2) inverter_3
    I75 (VDD VSS CLK net19) inverter_2
    I81 (VDD VSS net14 net24) inverter_2
    I77 (VDD VSS net18 net13) inverter_2
    I80 (VDD VSS net17 net22) inverter_2
    I79 (VDD VSS net13 net14) inverter_2
    I76 (VDD VSS net16 net15) inverter_2
    I78 (VDD VSS net15 net17) inverter_2
    I82 (VDD VSS net22 net21) inverter_2
    I83 (VDD VSS net24 net3) inverter_2
    I95 (VDD VSS net5 net7) inverter_2
    I94 (VDD VSS net6 net8) inverter_2
    I93 (VDD VSS net8 net20) inverter_2
    I92 (VDD VSS net7 net11) inverter_2
    I91 (VDD VSS net4 net6) inverter_2
    I90 (VDD VSS net3 net4) inverter_2
    I89 (VDD VSS net21 net1) inverter_2
    I88 (VDD VSS net1 net5) inverter_2
    I98 (VDD VSS net20 net9) inverter_2
    I96 (VDD VSS net12 net2) inverter_2
    I99 (VDD VSS net11 net12) inverter_2
    I97 (VDD VSS net9 net10) inverter_2
    I42 (CLK SW2 VDD VSS net16) nor_1
    I43 (net25 net19 VDD VSS net18) nor_1
ends non_overlap_gen
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: nand_1
// View name: schematic
subckt nand_1 A B VDD VSS Y
    M3 (net1 B VSS VSS) nch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 \
        sd=310n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
    M2 (Y A net1 VSS) nch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 \
        sd=310n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
    M1 (Y B VDD VDD) pch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 sd=310n \
        ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 nrs=0.3875 \
        sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
    M0 (Y A VDD VDD) pch_25_mac l=280n w=400n multi=1 nf=1 sigma=1 sd=310n \
        ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 nrs=0.3875 \
        sa=230n sb=230n sca=0 scb=0 scc=0 mismatchflag=1
ends nand_1
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: inverter_1
// View name: schematic
subckt inverter_1 VDD VSS Vin Vo
    M1 (Vo Vin VDD VDD) pch_25_mac l=280.0n w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M2 (net1 Vin VSS VSS) nch_25_mac l=280.0n w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M0 (Vo Vin net1 VSS) nch_25_mac l=280.0n w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
ends inverter_1
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: inverter_clk_comp
// View name: schematic
subckt inverter_clk_comp VDD VSS Vin Vo
    M0 (Vo Vin VSS VSS) nch_25_mac l=280.0n w=800n multi=1 nf=2 sigma=1 \
        sd=310.0n ad=1.24e-13 as=1.84e-13 pd=1.42u ps=2.52u nrd=0.19375 \
        nrs=0.19375 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M1 (Vo Vin VDD VDD) pch_25_mac l=280.0n w=400n multi=1 nf=1 sigma=1 \
        sd=310.0n ad=9.2e-14 as=9.2e-14 pd=1.26u ps=1.26u nrd=0.3875 \
        nrs=0.3875 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
ends inverter_clk_comp
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: clk_Comparator_mosLevel_test_2
// View name: schematic
subckt clk_Comparator_mosLevel_test_2 CLK VDD VSS Vin\+ Vin\- Vo\+ Vo\-
    S2 (Vy CLK VDD VDD) pch_25_mac l=1u w=1u multi=1 nf=1 sigma=1 \
        sd=310.0n ad=2.3e-13 as=2.3e-13 pd=2.46u ps=2.46u nrd=0.155 \
        nrs=0.155 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    S1 (Vx CLK VDD VDD) pch_25_mac l=1u w=1u multi=1 nf=1 sigma=1 \
        sd=310.0n ad=2.3e-13 as=2.3e-13 pd=2.46u ps=2.46u nrd=0.155 \
        nrs=0.155 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M7 (Vx Vy VDD VDD) pch_25_mac l=1u w=1u multi=1 nf=1 sigma=1 sd=310.0n \
        ad=2.3e-13 as=2.3e-13 pd=2.46u ps=2.46u nrd=0.155 nrs=0.155 \
        sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M8 (Vy Vx VDD VDD) pch_25_mac l=1u w=1u multi=1 nf=1 sigma=1 sd=310.0n \
        ad=2.3e-13 as=2.3e-13 pd=2.46u ps=2.46u nrd=0.155 nrs=0.155 \
        sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M3 (A CLK P VSS) nch_25_mac l=1u w=1u multi=1 nf=1 sigma=1 sd=310.0n \
        ad=2.3e-13 as=2.3e-13 pd=2.46u ps=2.46u nrd=0.155 nrs=0.155 \
        sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M4 (B CLK Q VSS) nch_25_mac l=1u w=1u multi=1 nf=1 sigma=1 sd=310.0n \
        ad=2.3e-13 as=2.3e-13 pd=2.46u ps=2.46u nrd=0.155 nrs=0.155 \
        sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M6 (Vy Vx B VSS) nch_25_mac l=1u w=1u multi=1 nf=1 sigma=1 sd=310.0n \
        ad=2.3e-13 as=2.3e-13 pd=2.46u ps=2.46u nrd=0.155 nrs=0.155 \
        sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M5 (Vx Vy A VSS) nch_25_mac l=1u w=1u multi=1 nf=1 sigma=1 sd=310.0n \
        ad=2.3e-13 as=2.3e-13 pd=2.46u ps=2.46u nrd=0.155 nrs=0.155 \
        sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M2 (Q Vin\- VSS VSS) nch_25_mac l=1u w=5u multi=1 nf=1 sigma=1 \
        sd=310.0n ad=1.15e-12 as=1.15e-12 pd=10.46u ps=10.46u nrd=0.031 \
        nrs=0.031 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    M0 (P Vin\+ VSS VSS) nch_25_mac l=1u w=5u multi=1 nf=1 sigma=1 \
        sd=310.0n ad=1.15e-12 as=1.15e-12 pd=10.46u ps=10.46u nrd=0.031 \
        nrs=0.031 sa=230.0n sb=230.0n sca=0 scb=0 scc=0 mismatchflag=1
    I23 (VDD VSS Vy Vo\-) inverter_clk_comp
    I22 (VDD VSS Vx Vo\+) inverter_clk_comp
ends clk_Comparator_mosLevel_test_2
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: DC_DC_Converter_Ideal
// View name: schematic
subckt DC_DC_Converter_Ideal VSS Vcfly1 Vcfly2 Vin Vout
    V5 (Vref VSS) vsource dc=Vref type=dc
    I15 (CLK1 CLK2 VSS Vcfly1 Vcfly2 Vin Vout) converter_core
    I19 (net4 CLK1 CLK2 Vin VSS) non_overlap_gen
    I11 (net1 CLK Vin VSS net2) nand_1
    I21 (Vin VSS net2 net4) inverter_1
    V7 (CLK VSS) vsource type=pulse val0=0 val1=Von period=1/fsw \
        rise=trans fall=trans width=D*1/fsw fundname="fsw"
    I30 (CLK Vin VSS Vref Vout net1 net3) clk_Comparator_mosLevel_test_2
ends DC_DC_Converter_Ideal
// End of subcircuit definition.

// Library name: DC_DC_Converter
// Cell name: Converter_hb_tb
// View name: schematic
I20 (0 net17 net20 0) Wire_Bonding_Model C_pcb=5p C_wire=500f ind=2n
I16 (0 net13 net7 net18) Wire_Bonding_Model C_pcb=5p C_wire=500f ind=2n
I13 (0 net11 net9 net16) Wire_Bonding_Model C_pcb=5p C_wire=500f ind=2n
I10 (0 net10 net14 net5) Wire_Bonding_Model C_pcb=5p C_wire=500f ind=2n
I5 (0 net6 Vout net5) Wire_Bonding_Model C_pcb=5p C_wire=500f ind=2n
I2 (0 net2 net1 0) Wire_Bonding_Model C_pcb=5p C_wire=500f ind=2n
I114 (0 net4 net3 Vin) Wire_Bonding_Model C_pcb=5p C_wire=500f ind=2n
C0 (net16 net18) capacitor c=Cfly
C1 (net5 0) capacitor c=Cout ic=600.0m
R23 (Vout net20) resistor r=Rload_10u
V3 (Vin 0) vsource dc=Vin pacmag=1 type=dc
I25 (net1 net7 net9 net3 net14) DC_DC_Converter_Ideal
 

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