jimjim2k
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hardware designing tips and tricks
Hi
Before simulating VHDL code behaviorally (we use Cadence Leapfrog VHDL) that is intended to be synthesized eventually, first get it to compile with Cadence Leapfrog (because we have many licenses for that), and then read it into Synopsys (only the Synopsys 'analyze' or 'read' command is necessary, you need not synthesize the design to get the important warning mentioned below) and look for warning and error messages.
This also includes several tips on writing synthesizable code, at least for Synopsys VHDL Compiler and Design Compiler.
1. h**p://www.arl.wustl.edu/~jaf/hardware/tips.html
* -> t
tnx
Hi
Before simulating VHDL code behaviorally (we use Cadence Leapfrog VHDL) that is intended to be synthesized eventually, first get it to compile with Cadence Leapfrog (because we have many licenses for that), and then read it into Synopsys (only the Synopsys 'analyze' or 'read' command is necessary, you need not synthesize the design to get the important warning mentioned below) and look for warning and error messages.
This also includes several tips on writing synthesizable code, at least for Synopsys VHDL Compiler and Design Compiler.
1. h**p://www.arl.wustl.edu/~jaf/hardware/tips.html
* -> t
tnx
