Hardware design of 3MB/s point-to-point data link..

[Buriedcode]

Hi.
I've posted many questions in this board, and have received many useful reply's. I thank you. Here's my next problem.... :?

Basically I've designed a simple protocol on CPLD's for a 3MB/s data link using manchester encoding (1byte preamble, 2 bytes data, 1 byte tail). The CPLD's are fine, otherwise I would have posted this in the FPGA area. It works fine in simulation (lattice ispLEVER has a pretty good timing function on it, reporting scew, and prop delays) My problem is, the interface.

Its going to be wireless, but, as a test, I just want to sort out the baseband, so I tried connected the two CPLD's together with 2 wires. Pin to pin. Data, and GND. I knew it wouldn't work, although the wires a very simple solid core, hook-up wires each about 3cm long. I'm gonna try getting hold of some CMOS schmitt triggers, to clean up the clocks on both CPLD's, and the data for the receiver.

Any other suggestions?? I'm aware of the RS protocols, but they're all about distance (+50 feet). I just need a simple way of connecting them.
Remember its 1.536MB/s manchester encoded, so its basically like sending 3.072MB/s (1.5Mhz bandwidth?).

Any hints are welcome. As I said, its for a test prototype, so its nothing permenant.


BuriedCOde.

 

[batdin]

If everithing is fine (as you state) the problems may be:
- mismatched levels (receiver expects lower level than received but aren't levels logical ???)
- signal polarity
But my magic Crystal Ball says something else is wrong.Not the connection.

 

[flatulent]

One test to do is have the same data sent repeatedly and examine the wires with an oscilloscope. If you set the sweep rate properly you will get just one packet across the screen and be able to see glitches and levels. If you are fortunate enough to have a digital storage scope use the one sweep capture mode.

 

[Buriedcode]

Hi again,

Batdin, its funny you mentioned signal levels, thats been bugging me for a while. You see my logic probe I use (homemade, TTL, but it does the job) gives a fair indication of things.

If I connect the logic probes power leads to 'either' boards power, and then probe the data wire from Tx to Rx, something interesting occurs. At the Tx, the red LED and yellow LED is on. Inplying that theres a '1' present, and a transition. But at the recievers end, the green light glows faintly as well. So I think the levels (Ground) are not exactly level, EVEN THOUGH they are connected with another wire with a tiny resistance (0.4ohms). As I said, its a real cheap, ugly setup, but hey :roll: I have no money for an oscilloscope, or new PCB's to be made (to include interface RS422/485 stuff), still, it seemed a great idea in theory).

I 'did' however get to use one when I had a previous version of the design software (the CPLD's were programmed with different versions), back when I used a basic UART, 'simplex' protocol, with start/stop. The signal looked clean, they all did except the CLOCK which had an overshoot that planes could land on but thats fixed now.

Have either of you (or anyone) managed to link two CPLD's/FPGA's simply, with a PCB trace or a cable, at high speed??? >2MB. If so I'd love to know the specifics, because now I'm starting to doubt that my manchester encoder/decoder I used work, they were both schematic entry design and work a treat in simulation.

Sorry for going on, but I've solved any possible 'power' issues. I found something on the data sheet for the devices about 'low-power' mode for low speed apps (<10Mhz). Both chips now draw less than 15ma each, about 85ma less than they did before (I own 4 burnt out 7805 regulators ).

Thanks again, your suggestions are always useful.

BuriedCode.