Handling multiple grounds in mixed signal PCB

[checkmate]

stripline ground plane vias

I've read numerous articles on how grounding in mixed signal PCBs should be handled, and I've observed the following 3 camps.
1. Solid ground with split power plane or power traces.
2. Split digital/analog ground plane, with star-point at power supply.
3. Split digital/analog ground plane, with star-point near to the mixed signal chip.

I'm designing a mixed-signal 4-layer PCB involving a BGA IC with both analog (tv and audio signals) and digital pins partitioned across the IC itself, ie analog and digital pins are more or less partitioned on the chip. The design recommendations were to use a split ground. I've seen app notes which recommend either placing ADCs across the split ground, or entirely in the analog ground by virtue that they consume less current. But my chip is a mostly digital processor with significant current consumption (arnd 100mAs).

The following are my questions.
1. Which grounding scheme (from the above 3) should I use? If split, where should be the recommended star point?
2. Should I place my IC over the analog ground, digital ground, or over the split?(considering the fact it's a 0.1mm pitch BGA, and hence placing over a split ground would mean very narrow separations between the 2 grounds)
3. How should we handle digital control traces that will have to route across the split planes?

 

[Uky]

You are likely to find as many answers as you have listed the different schools... My experience from RF and Analog engineering considering signal integrity is to use one single solid ground plane in one of the inner layers. From the cellular industry, this is what I would have done:

1. Designate one inner layer as ground plane.

2. Place your [IC] components.

3. Ground all "GND" BGA balls.

4. Connect all "VCC"´s to a supply voltage plane. If you have multiple supply voltages, you may use split planes. These planes should reside next to the GND plane layer.

5. Decouple all supply pins.

6.Having all GND and supply pins routed, you may the proceed with the signals.

7. At earliest convenience, try to get down on an inner layer. (Explanation will follow)

8. Try to separate analog and digital signals on different layers. Check that proper impedances can be obtained. NEVER route an impedance sensitive trace through an area where a split-plane exists. If you will have to do this, you MUST create a stripline in the inner layers, and this trace must have ground plane vias stitched on both sides, thus providing a "coaxial" run inside the board.

(You may have to use micro-vias for this.)

9. When all traces are routed on inner layers, Pour copper on top and bottom layer, connect to "GND".

10. Stitch the ground planes together with multiple vias at the board edges.

This procedure ensured a "first board success" on a PMG device layout.

 

[checkmate]

Many thanks for the advice. I understand that there are many camps out there, therefore I'm not looking for additional books or application notes, as I understand that many of these stuffs are not always written by people on the ground doing the actual design and facing the actual problems. Therefore, I just want to know the design preferences of actual pcb designers.

For point 7, do you mean that it's better for signals to run on the internal planes rather than the top/bottom layers?

 

[House_Cat]

You might want to take a look at:
**broken link removed**

Pages 23-26 of this presentation give a good summary of current thinking regarding ground planes based on properly done signal analysis and experience.

Controlled impedance for very high frequencies is more difficult on inner layers than on top and bottom layers because variations in dielectric thickness are more difficult to control on the inner layers. Burying the signals on inner layers does not improve the signal integrity as a general rule - each via represents a series inductance, and inner layer traces have higher path delay (read signal attenuation and delay) than surface traces as a result of the board dielectric on both sides of the trace. Both of those factors, along with the trace impedance variations, degrade signal integrity. That having been said, if the surface of the board is exposed to E field noise sources, burying the traces on inner layers provides some degree of shielding - it does almost nothing for magnetic field noise sources. The only reason to bury signal traces is for some improvement in E field emission control that can be achieved by using board layers as shielding - i.e. radiated signals from the board (EMC).

Likewise, copper flooding the top and bottom of the board is only useful for EMC. It does virtually nothing to improve the signal conditions on traces within the board. In fact, copper flooding can give rise to local resonant loops at harmonics of clock edge signal components, and can cause unwanted capacitive coupling of high frequency RF into more sensitive parts of the circuit. In general, copper flooding should only be done after careful modeling of the circuit with a reliable 2.5d or 3d modeling program for high frequency or fast edge rate boards.