Handling large vectors in VHDL?

KrishKrishnaa · Aug 7, 2024

I'm new to FPGA designing. I'm working on a project where I'm handling large vectors for a certain application (pattern matching).

Code VHDL - [expand]
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Generic (        
N : integer := 128;
M : integer := 128;       
SAMPLES : integer := 128  -- Number of samples        );
Port (        clk : in STD_LOGIC;  
reset : in STD_LOGIC; 
 pattern_1 : in STD_LOGIC_VECTOR(SAMPLES * N - 1 downto 0); 
 pattern_2 : in STD_LOGIC_VECTOR(SAMPLES * M - 1 downto 0);
Result : out STD_LOGIC_VECTOR(SAMPLES * M - 1 downto 0)         );

I want to see how large the vector size can be accommodated on the FPGA based on the available resources (meaning the N, M, and SAMPLES are not restricted to 128). I know using them in the entity will not be ideal as we cannot map these large vectors to the FPGA IO pins; what will be the best way to handle this? I'm using the Nexys4 FPGA board.

barry · Aug 7, 2024

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KrishKrishnaa said:
I know using them in the entity will not be ideal as we cannot map these large vectors to the FPGA IO pins.

I don’t understand this statement. If you don’t have enough pins to match the number of bits in your vector, then you have to break those vectors into smaller chunks, and load the chunks sequentially and then reassemble them internally.

Handling large vectors in VHDL?

KrishKrishnaa

Newbie

barry

Advanced Member level 7

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Handling large vectors in VHDL?

KrishKrishnaa

Newbie

barry

Advanced Member level 7

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