half cycle paths violaations in STA

Hi,

In my current project, I am seeing some half cycle paths (SETUP Violating paths). Now I shouldn't do any placement etc.

How can I fix those half cycle violating paths...

In data paths ,doesn't have more no .of logic levels. 2 to 3 levels of logic.

skew is also under limit.

please help in this regard.

is the half cycle path intended? is the path from clock gater or is it like ram->latch->reg etc? where do you see this violation first? end of synthesis or placement or cts etc? depending on where you see, you would have to take the appropriate action..

you would have to add few more lines of sdc like add negative latencies at enable to get the clock early and let the tool optimize that..you would have to study the path first...

Hi Kbulusu,

Thanks for ur quick reply.

This path is reg to reg path only.
It is not clock_gating group also.
It is after route opt stage.
I am seeing this type of violation in STA report.
I have to fix this violation.
Can we ignore the these half cycle path violations ? If we ignore what r spl cases to ignore those half cycle paths?
And how to check the SDC, weather those constraints r correct or not ?

what should we have to check in SDC ,before starting the PnR flow ?

Thanks in advance
qual_ti

no path violation should exist before TO...all paths regardless whether full or half-cycle should meet timing..now your design team might waive this if they determine that this particular half path is never exercised ..
Please determine where this half cycle path viol first shows up? it might exist in synthesis but might have met timing and so you wouldnt have noticed..if its in synthesis stage you saw, then its mostly likely 1. design issue -> check with designer/design
2. SDC issue -> check the clock relationships of launch/capture and if any phase inversion happens etc ...optionally multi cycle them if your design allows it...3. check if its going through a latch and it is transparent or the enable is constrained correctly..
3. make sure no skew or -ve latency constraints are set on the clock pin of flops to bring clock early at that point...
4. If nothing helps...trace the clock backwards from the flop and see if all clock phases are arriving as expected...

If you see this only after placement, then its likely a placement issue -> check the coordinates and net length ...
if its after cts..check the insertion delay/latency first and skew later...skew balancing will only make it worst as it adds skew buffers to balance the clocks (to minimize local skew)...

you would have to look sdc in conjuction with the design and timing reports to determine if everything is looking correct ....

hope this helps..

thanks a lot kbulusu.............