[SOLVED] [Guide Me] To use FMC in sp605

Thread starter sanju_
Start date Jun 27, 2011

Status: Not open for further replies.

Jun 27, 2011

sanju_

Full Member level 3

Hi all..

I am using spartan-6 sp605 to which i have connected FMC-105-DEBUG..
using edk(xilinx) i want to do one pin in j1 (J1: 20 pin x 2 row male header) as clock as output...
or using same software test iic eeprom(2kb inside fmc) in FMC..
just for understanding purpose...

my question is what are the things i have to include in edk and proceed...
any expamples or links about fmc please tell me.

thanks.

Status: Not open for further replies.

Similar threads

E
Terasic D8M-FMC Camera Module No UserGuide ?
- Started by embeddedesigner
- Feb 26, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
E
Which simulator should I use for verilog?
- Started by electronicslab
- Oct 26, 2024
- Replies: 9
PLD, SPLD, GAL, CPLD, FPGA Design
A
User Testbench for Core1553BRT_APB in LiberoSoc
- Started by Altair99
- Sep 12, 2024
- Replies: 3
PLD, SPLD, GAL, CPLD, FPGA Design
AMD 7Series FPGA Configuration Debugging (INIT_B and DONE pins use)
- Started by dpaul
- Feb 23, 2024
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design
H
How to store Coco training data set in Pynqz2 board
- Started by hudda
- May 25, 2024
- Replies: 1
PLD, SPLD, GAL, CPLD, FPGA Design

[SOLVED] [Guide Me] To use FMC in sp605

sanju_

Full Member level 3

Similar threads

Privacy & Transparency

Privacy & Transparency