OK, I think these with primary separation is OK yet, than all secondary lines/coopers as C4/C5 + & - to D3/LPF & Vout connecting make pls with really thicker/wider coopers!
Only a Via for layers changing between C4 & LPF is surly not reliable(even; if hole diameter is i.e. 1mm)_you can have minimum a double via right side of CPF, I would youse a spetial Via for that (I call PwrVia, with i.e. 0.7mm diameter)!!
D3 likes cooper surface by some higher currents (COOLING)/or minimum wider cooper lines on both contacts...
BTW: whats your output power/current pls?
I would change D1/R1 with CPF_& yet same Via problem as above!! Its place is near to the output connection.I would shift the T1 to top & on the ex place of D4 have a Y2 capacitor_I believe taht you must have it_minimum forseeing is needed!
If T1 is moved to top, you can slightly move it to right to (towards C4/C5); than you can have D2 between C1 & T1_with TP4 between both Diodes...
Apropo`s Testpoints:
You have a TP1, between CMC1 & D1, but where is hes reference pls!?
Its not referencable to the primary "GND"(called TP3 in your design)_it NEEDS an EXTRA TP for referencing on the other AC points of D1...
If you have higher current in these design_it need a heatshink on U1 too!
To finish: be care pls with positioning of all "Ref-Designators"!! Momentan are their relative RANDOMLY!_ a programmed failure source for miss populating/ testing on wrong point, needed overtime because you have lot of do to find the physically right component to the schema...
K.