GPIO Daughter Board Design

Hello guys,

I'm a hobbyist mostly into software engineering, in addition into doing stuff on my DE2-115 Cyclone IV FPGA development board.
Unfortunately I have only rudimentary skills on electronics and analogous systems...

Anyhow, I recently made a wirespeed Ethernet packet sniffer on my development board, all pure logic - no CPU, big fun. I want to extend on that.

To learn a bit in the electronics area my goal now is to make a GPIO connected Daughter Board for the dev-kit, with a couple of Ethernet PHY's on it.


I've collected some information and installed TinyCAD for initial schematics.

GPIO header details from the DE2 manual:


The PHY chip I want to use: **broken link removed**

Some manufacturer notes regarding power:
https://ww1.microchip.com/downloads/en/AppNotes/ANLAN206.pdf
(I've opted for a solution as in Figure 11)

And finally, my initial schematics for power rails!

(Please forgive my newbie mistakes)

I have a couple of questions that I would really appreciate help with:
- Since I'm not using the internal LDO, can I drop connecting it?
- Do I still need capacitors close to the power pins on the PHY chip? (As in Figure 7 from the app notes)
- What is the recommended way to wire up the DVDDH 3.3V?


With best Regards,

/stride

YES you need decoupling caps next to the power pins, they are critical for digital devices.
As to the rest follow the data sheets recommendations to the letter...
Layout and power system will be critical for proper operation of this device its a gigabit Ethernet transceiver...
Further when doing layout for these devices the board layer count has been usually 8-14 layers, occasionally I have done layouts on 6 layers, most were power and ground and would think that for best signal integrity and power distribution 8 layers in the minimum.

marce said:

YES you need decoupling caps next to the power pins, they are critical for digital devices.
As to the rest follow the data sheets recommendations to the letter...
Layout and power system will be critical for proper operation of this device its a gigabit Ethernet transceiver...
Further when doing layout for these devices the board layer count has been usually 8-14 layers, occasionally I have done layouts on 6 layers, most were power and ground and would think that for best signal integrity and power distribution 8 layers in the minimum.

Click to expand...

Thanks for the tips

I managed to find this excellent article regarding it, http://www.interfacebus.com/Design_Capacitors.html
Hopefully I'll figure it out!

As a start I'm focusing on understanding the power-net's and their requirements, the capacitors needed and how this could be laid out on the board.

Is it common to put one "power-net + ground islands" on separate layers? One for each power-net needed?
When placing a chip, can the individual pins terminate at the appropriate layer underneath?


I know, newbie questions... It's my first hardware design so please forgive me my stupid questions


/stride

One thing there are no ground islands there is one ground and there should be one unbroken ground plane at least...

- - - Updated - - -

Depending on how the chips power is distributed around the device you may get two voltages to a device on one layer... With QFN and similar devices you can place the decoupling caps on the bottom layer and have one supply going round the outside of the device and one supply going to the inside of the device.
Use power planes as these with the decoupling caps will give you the lowest impedance and if paired with a ground plane will give some planar capacitance helping things even further.
Have a look on the internet for "decoupling capacitors" and "power delivery integrity" you should find some interesting links and info...
I may not reply now for a while as I am having a big op (radical cystectomy) on Friday so expect to be a little unwell and off line for a while.