Good Clock frequency for General Purpose FPGA design

[digi001]

I'm looking for what would be a good clock frequency for a general purpose FPGA design. The FPGA currently preforms some basic counting and sequencing for industrial control functions but could expand to future field applications where necessary. Currently it uses a 37.5Mhz clock from a DSP that resides on the same PCB, but I'd like to add one more for standalone operations.

Would 10Mhz or 20Mhz be a good choice?

 

[shaiko]

That depends.
What is the fastest frequency you intend to run future designs at?
If it's a large FPGA, with many registers I'd pick a much faster clock - In the range of 150 Mhz.

 

[digi001]

Cant I always multiply up a 20Mhz to 150Mhz? The FPGA I am using has 3 built in PLLs.

 

[shaiko]

You can, but why should you?
Lowering the speed is easier than accelerating it.

 

[digi001]

True but lots of high speed clocks on a PCB can sometimes cause EMI issues?

 

[shaiko]

Not really.
You do need to take special care of high speed signals however.
It's the rise/fall times you should look at when analyzing signal integrity issuse - not the direct frequency.

If you worry about radiation, you can route the signal as a microstrip (not a stripline).
Use proper terminations and keep the trace as short as possible.