Two models exist for timing simulation of digital circuits. One is transport and the other is inertial. As far as I understand, a signal cannot propagate through a gate level component if the input to it has a duration shorter than its propagation delay. The inertial delay model is perfect for this situation. So why should we need the trasport delay when doing simulation of real circuits?
The more important question is related to +pulse_e and +pulse_r switches found in ModelSim and QuestaSim.
For pure intertial delay we can use +pulse_e/100 and +pulse_r/100, reject all pulses below 100% propagation delay.
For pure transport delay we can use +pulse_e/0 and +pulse_r/0, accept all pulses that are more than 0% of propagation delay.
Why then would one want to use something like this which generates X at outputs: e.g +pulse_e/70 and +pulse_r/30, reject all pulses below 30%, generate X for pulses between 30% and 70%. Accept all pulses above 70%. Why not just use the purely inertial model +pulse_e/100 and +pulse_r/100? Why use a model that can generate X at the output of gates? I thought that the purely inertial delay was closest to real world.