Glitching at the output OPA197 unity gain inverting amplifier

[newbie_hs]

I am designing a unity gain inverting amplifier using OPA197.The input is a square wave of amplitude 8V peak to peak and a frequency of 50Khz.
Please find the attached circuit.
May I know why it is happening

 

[KlausST]

Hi,

An OPAMP is made for analog signals. But your input is a digital signal.
While one can use a digital signal to test a step response, stability and overshoot .. it usually is not very useful as signal in a true application.
Many OPAMPs suffer from input stage saturation .. often causing much wores output signals.

If you read the datasheet .. you already see the overshoot at a step response. There are diagrams.
For sure the overshoot is different if you have different conditions (different supply voltage, different input signal levels, different load, different resistor values..)

If you read the datasheet .. you will see the "slew rate" specification. It also tells you that an OPAMP can not follow extremely steep input signals.

****

I usually put an RC LPF in front of the OPAMP input to avoid input stage saturation .. and thus distortion, ringing, DC drift ...

Klaus

 

[danadakk]

https://www.ti.com/lit/pdf/slyt087

https://www.analog.com/media/en/technical-documentation/application-notes/an148fa.pdf

OpAmp input C also problematic. Cure is small amount of fdbk C. You can derive optimal Cfdbk thru LaPlace analysis,
signal flow graph probably easiest due to number poles in T(s) of the internal/external transfer function. There are tools
on web to make that easy. Dotted line in output graph is for Cfdbk = 0, eg. the ringing case you observe.

The following excellent treatment of problem -

https://ocw.mit.edu/courses/res-6-010-electronic-feedback-systems-spring-2013/098e108c53516237f989968f10f7f6aa_MITRES_6-010S13_chap03.pdf

Below dotted line graph Fdbk C = 0, otherwise 6 pf

Regards, Dana.

 

[newbie_hs]

https://www.ti.com/lit/pdf/slyt087

https://www.analog.com/media/en/technical-documentation/application-notes/an148fa.pdf

OpAmp input C also problematic. Cure is small amount of fdbk C. You can derive optimal Cfdbk thru LaPlace analysis,
signal flow graph probably easiest due to number poles in T(s) of the internal/external transfer function. There are tools
on web to make that easy. Dotted line in output graph is for Cfdbk = 0, eg. the ringing case you observe.

The following excellent treatment of problem -

https://ocw.mit.edu/courses/res-6-010-electronic-feedback-systems-spring-2013/098e108c53516237f989968f10f7f6aa_MITRES_6-010S13_chap03.pdf

Below dotted line graph Fdbk C = 0, otherwise 6 pf

View attachment 198039


Regards, Dana.

May I know how you get 12p.

I tried the equation given here page no 17 .I got 6pf,but it's not working

 

[danadakk]

I did not compute (lazy), just tried a value.

Note here also how OpAmp loses control of virtual ground both when slewing
and due to finite bandwidth, but is also helped with Cfdbk, does not fix slewing
problems, if anything aggravates it (effective response) a little (slewing causes
OpAmp to be non linear for slew time , many papers on web about this).

 

[newbie_hs]

I did not compute (lazy), just tried a value.

Note here also how OpAmp loses control of virtual ground both when slewing
and due to finite bandwidth, but is also helped with Cfdbk, does not fix slewing
problems, if anything aggravates it (effective response) a little (slewing causes
OpAmp to be non linear for slew time , many papers on web about this).

View attachment 198040

Thank you...
I reduced the resistors value to 2K.Then I observed no ringing.

 

[danadakk]

Note I changed Cstray at NI input to 5 pF, thats more representative in layouts. So that caused
Cfdbk to be more like the 6 pF I finally used.

Of course your Zin will change.

Regards, Dana.

 

[KlausST]

OpAmp input C also problematic.

Here the C2 does not work as RC LPF, because the node is virtual GND.

So you are right, the C in the feedback is an improvement.

Even better would be: signal_input -> R1 -> C2 to GND --> R2 --> Inverting_input
Where R1 and C2 build the low pass ...
But for (DC) gain calculation one needs to use (R1 + R2) as input resistor

Klaus