Glitches in a current steering DAC

Hello,

In a current steering DAC I designed there are glitches due to the switching transistors. I use some DACs in my delta sigma ADC, the current of the first DAC varies slightly due to the glitches, i.e if it's supposed to be 8.5uA, it would be 8.7uA right after the switching and the it settles to the steady state, which is 8.5uA. I used low-swing, high-crossing switch drivers for controlling DAC switches, to decrease the glitche, which actually helped a lot. But my last DAC, which provides a few hundred nano amps would be significantly affected by those glitches, i.e if the current is supposed to be 100nA, it reaches to 400nA at the switching time and then reaches to 100nA. The switching circuit I used for the last DAC is just the one I used for the first DAC, but since current is less, that glitch screws the current. Since the last DAC in delta sigma ADC is not as important as the first one, I thought those glitches may not be big deal, but now I get a warning from simulation software that transistors used in a stage after that last DAC would be melted due to exceeding Imelt. I appreciate if someone help me with this problem.
Tnx

The old current DACs I worked on, were designed to
source-steer the current rather than gate-switch it -
this had (in the day) the lowest glitching and fastest
settling.

dick_freebird said:

The old current DACs I worked on, were designed to
source-steer the current rather than gate-switch it -
this had (in the day) the lowest glitching and fastest
settling.

Click to expand...

Thanks for your post. I didn't get it, what structure it is? I haven't heard it before, I appreciate if you give me more information about it, or some papers or so.

The scheme used NJFET diff pairs and wasted current away
from the R-2R ladder into VCC for bits that were "off". The
signal swing required was a couple of hundred mV and was
applied to the "wasting" device gate, so the "active" bits'
gates were pretty much static - no movement, nothing to
settle. Unlike hard-switching the JFET (a volt or more, VPO)
or a MOSFET (couple of volts, plus even nastier Miller cap).

I don't know of any papers. I worked on the part as a
designer at the manufacturer (I am no longer there). But
I suspect that the scheme was not invented there, and
there may be other old DACs using differential switches
that could be equally informative and more accessible.

Another option, used sometimes in chop-amps and other
switched / switched-capacitor circuits, is "glitch compensation".
If your problem is Miller charge with nowhere to go (esp. the
turn-off edge, pretty much has to head on out the drain
since the source has cut off) an opposite phase clock and
an appropriately-scaled capacitor coupling it to the problem
node, might knock 90% or so of the glitch energy back out.

Thanks for your description. It seems the method you mentioned is not for current steering DAC, it's for R-2R ladder DAC. Anyway, in a current steering DAC, each current cell has two control switches (B, and Bbar), and depending on the value of that bit, current would fellow through either one of those switches, so I think "wasting" device cannot be used here.

BTW, I know what the source of problem is, but I cannot solve it, at least for my last DAC. The problem is due to the signals controlling switches (B, and Bbar). Those two signals neither should be overlapped, nor non overlapped. So they should have high crossing points, otherwise there would be big glitches in the current, and I believe that's because drain node of the current source would be discharged at any transition level. Using low-swing high crossing signals would help a lot to decrease those glitches. But for the last DAC, in my case, since current is so less, it means even slight changes in the voltage may result in big variations in the current.

Last point you mentioned is dummy switch I think, isn't it? That's interesting that I have seen it everywhere that dummy switch would help, but I don't know why when I simulate the circuit with dummy switches I cannot see any difference. Even in some papers I've seen it's better not to use dummy switches, since size of switches cannot be minimum anymore.