Clock feedthrough probably. Hard slappin' the gates
means injecting clock noise. Imbalance in N vs P VT
or imbalance in phase drive might account for the offset
seen after the glitches (the C-V curves probably differ at
least a little, gate capacitance transfers to S, D, B
differently as you traverse the gate swing).
Steering source current can work with lower swings and
less harsh events.
I'd go drag a rake through the switches and the current
sources / sinks they steer, looking at symmetry.