Glitch problem o differential transmission gate in cadence

[PhdSA]

I'm designinig a 3 bit binary differential current steering DAC using differential tansmission gate as a switch.
Below the architecture of the differential switches:

I do the layout in cadence of this subcircuit, however there are a glitch which produce distortion of signal.I need some advices how to connect the binary input (in1n and in1p) in orde to reduce the glitch and avoid distorsion of signal as seen in figure below

 

[dick_freebird]

Clock feedthrough probably. Hard slappin' the gates
means injecting clock noise. Imbalance in N vs P VT
or imbalance in phase drive might account for the offset
seen after the glitches (the C-V curves probably differ at
least a little, gate capacitance transfers to S, D, B
differently as you traverse the gate swing).

Steering source current can work with lower swings and
less harsh events.

I'd go drag a rake through the switches and the current
sources / sinks they steer, looking at symmetry.

 

[PhdSA]

Clock feedthrough probably. Hard slappin' the gates
means injecting clock noise. Imbalance in N vs P VT
or imbalance in phase drive might account for the offset
seen after the glitches (the C-V curves probably differ at
least a little, gate capacitance transfers to S, D, B
differently as you traverse the gate swing).

Steering source current can work with lower swings and
less harsh events.

I'd go drag a rake through the switches and the current
sources / sinks they steer, looking at symmetry.

Hello,
The problem of glitch does not appear when simulating schematic in cadence as you can see: below

However, the glitch appears whan i do the layout of this subcircuit. I try to do symmetrical layout. What can i do have symmetrical input with the same capacitance gate .
Give me some advices to do a good layout to avoid the glitch. I'm so gratefull.

Best Regards

 

[dick_freebird]

Then it sems that layout parasitics are the source of charge injection asymmetry (assuming that LVS is clean for explicit-device param match).

Look at routing for mismatched lengths which will unbalance parasitics. In doing a clocked comparator piece-part design using switched capacitors I found millivolts of offset in the stubs' route asymmetry, improved by balancing the extracted parasitics by adding dead length to the shorter runs.

 

[PhdSA]

Then it sems that layout parasitics are the source of charge injection asymmetry (assuming that LVS is clean for explicit-device param match).

Look at routing for mismatched lengths which will unbalance parasitics. In doing a clocked comparator piece-part design using switched capacitors I found millivolts of offset in the stubs' route asymmetry, improved by balancing the extracted parasitics by adding dead length to the shorter runs.

Thank you very much. Thus, i resolve the problem of glitch due to asymmetry of the binary input'path. However, i face an other problem, the differential signals do not always intersect at their midpoint, the operating point is variable. How can I solve this problem? taking account that with simulation the two curves have usually the same midpoint, which is not the case when i do the layout s you can see below:

-Curves after layout

 

[dick_freebird]

This is probably just more fine-match layout detail, but you
may also have P vs N mirror (?) fidelity or flip-delay skew
(how do you split phases where you need true and complement,
like all your switches' gate nodes)?

Getting a phase-split to produce two dead aligned edges over
all conditions is impractical. "Good enough" may be achievable.
But do you know what's "good enough" other than by the full
chain qualitative outcome?

Everything starts to matter, work backward to where "things
first start to come apart" in timing, settling, pulse-phase flat top
value, etc.

 

[dick_freebird]

Your ramps are nonlinear to the eye (and that's on my phone screen). What happens at the 1/4 and 3/4 (roughly or exactly, would itself be a clue) points? Big glitch energy and change of slope. Is the ramp expected to be linear end-to-end or are the impulses artifacts of start and stop endpoint activity? Pretty filthy for a data converter I think, anyhow. What are the impacts of these artifacts to accuracy of nearby codes? That would be your "care-about index" I suppose.

 

[PhdSA]

Your ramps are nonlinear to the eye (and that's on my phone screen). What happens at the 1/4 and 3/4 (roughly or exactly, would itself be a clue) points? Big glitch energy and change of slope. Is the ramp expected to be linear end-to-end or are the impulses artifacts of start and stop endpoint activity? Pretty filthy for a data converter I think, anyhow. What are the impacts of these artifacts to accuracy of nearby codes? That would be your "care-about index" I suppose.

Despite i enhance the glitch, the gap between the two curves in the midpoint is increased, they not always intersect at their midpoint as seen in figure below. how can i make the two curves symmetrical and intersect in the middpoint when doing the layout

 

[sidun.av]

Despite i enhance the glitch, the gap between the two curves in the midpoint is increased, they not always intersect at their midpoint as seen in figure below. how can i make the two curves symmetrical and intersect in the middpoint when doing the layout

Maybe you can share a screenshot of your layout with important nets marked? I think it would be easier to help then.
Also, did you inspect parasitic capacitances/resistances using Calibre? Did you compare schematic/layout currents?
P.S. What is the tech node and vendor that you are using?