Glitch free tristate?

[TQFP]

Greetings,

I am trying to move my two-process FSM to a single process FSM to have a "more modern" style, but code that was working is now crapping out. Will my tristate signal be solid or will it glitch when set up like this?

Thanks,
Matthew

port (
  cd : inout std_logic_vector(7 downto 0);
 . . .

architecture . . .
  signal tristate : std_logic;
  signal data_reg : std_logic_vector(7 downto 0);

  process(clk)
  begin

    tristate <= '1';
 
    case state is
      when st_2 =>
         state <= st_2;
         data_reg <= . . .

      when st_2 =>
         -- tristate enable only in st_2
         tristate <= '0';
         if other_signal = '1' then
           state <= st_3;
         else
           state <= st_2;
         end if;

      when st_3 =>
. . .
end process;

cd <= data_reg when tristate = '0' else (others => 'Z');

 

[shitansh]

Hi,

Since your tristate signal changes on clock edge it is glitch free.

HTH

 

[FvM]

Look sharp! The FSM can't work, because it misses an edge-sensitive condition.
You may want to think about VHDL basics before creating a new "modern style".