Zdenko Janoska
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Hi dear friends,
about "glitch free clock multiplexing" I read a lot of topics already. But one problem is still concerning me.
I have to switch from one to the another one asynchronous clock as positive edge source of the shift register. All problem is drawn in attachment. Signal 'select' is synchronized with clk1. It can by synchronized on positive or negative edge. 'Clk2' is asynchronous clock.
In the first stage shift register is clocked by 'clk2' - equal or slower frequency then 'clk1'. 'clk1' is stopped due to energy consumption and therefore 'clk2' can not be synchronized by 'clk1'. Then 'clk1' is start and signal 'select' is toggle. The problem is, that I can not wait for finish all period of 'clk2' - because it can be various time long. I have to stop it and run 'clk1' as source for shift register. I can wait for one or max two periods of 'clk1' but the time has to be the same in any cases to source the shift register from 'clk1' - other devices will wait for data in exactly time.
Do you have any ideas how to manage this use? This design is in 150nm technology and has to be optimized for power and area therefore this design can seem strange for someone.
Thank you very much in advance.
Best regards,
Zdenko Janoska
about "glitch free clock multiplexing" I read a lot of topics already. But one problem is still concerning me.
I have to switch from one to the another one asynchronous clock as positive edge source of the shift register. All problem is drawn in attachment. Signal 'select' is synchronized with clk1. It can by synchronized on positive or negative edge. 'Clk2' is asynchronous clock.
In the first stage shift register is clocked by 'clk2' - equal or slower frequency then 'clk1'. 'clk1' is stopped due to energy consumption and therefore 'clk2' can not be synchronized by 'clk1'. Then 'clk1' is start and signal 'select' is toggle. The problem is, that I can not wait for finish all period of 'clk2' - because it can be various time long. I have to stop it and run 'clk1' as source for shift register. I can wait for one or max two periods of 'clk1' but the time has to be the same in any cases to source the shift register from 'clk1' - other devices will wait for data in exactly time.
Do you have any ideas how to manage this use? This design is in 150nm technology and has to be optimized for power and area therefore this design can seem strange for someone.
Thank you very much in advance.
Best regards,
Zdenko Janoska