Giving reference for Signals in PCB design

[gowthaman90.d]

Hi all,

I have a doubt in giving the reference to the signals in High speed PCB. I am working on 16 layer board. My stack up is as below. I have a plan to route the high speed signals in L3. There is continuous GND plane in L2 but I cant give continuous power plane in L4 as the designs have many powers. My high speed signals are crossing over the split power planes in L4. I know the return path of the signals will take the least inductance path.

Will the Split planes in L4 affects the Impedance and Return of the signals in L3?. Experts pls clear me on this.

L1 - TOP

L2 - GND(Continuous plane with no split)

L3 - SIGNAL1 (High Speed Signals Routing)

L4 - PWR (Split power planes)

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.

L16

 

[FvM]

The question can't be answered generally. In many cases it's OK to use split power planes as ground for embedded strip lines or differential pairs. I did it quite often in mixed signal designs, there are however some prerequisites:

- power planes have multiple low inductance bypass capacitors distributed over the board area
- power nets don't carry large noise level
- embedded strip lines shouldn't be placed along the plane gaps