Deka87
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Good Morning to everybody.
I'm training to understand the Back-end process of digital implementation using Encounter.
In order to understand the design flow, I'm training to implements a simple verilog code. But I've a problem, when I want to P&R core, based on two only standard cell, and the connection to IO PAD.
I've created a Verilog file (chip.v) in which there are the PAD name modules (provided by the foundry) and the name of the input ports and ouput ports of the core.
When I've imported the design in encounter, (using verilog of the chip, standard cell lef file, pad lef file and ioc constrain). The output and input of the core block are connected to a triangle pins and,while, they aren't connected to the pad.
Is there any one can help me?
I'm training to understand the Back-end process of digital implementation using Encounter.
In order to understand the design flow, I'm training to implements a simple verilog code. But I've a problem, when I want to P&R core, based on two only standard cell, and the connection to IO PAD.
I've created a Verilog file (chip.v) in which there are the PAD name modules (provided by the foundry) and the name of the input ports and ouput ports of the core.
When I've imported the design in encounter, (using verilog of the chip, standard cell lef file, pad lef file and ioc constrain). The output and input of the core block are connected to a triangle pins and,while, they aren't connected to the pad.
Is there any one can help me?