counterboy
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hi, i am new to VHDL and after writing the code below i get the error -Signal <> cannot be synthesized, bad synchronous description.- can someone help and tell me where im going wrong
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity delaytimer is
port( clock:in std_logic;
delay:in integer range 0 to 15;
delayF:out std_logic
);
end delaytimer;
architecture Behavioral of delaytimer is
signal lag:integer range 0 to 15;
signal clock1: std_logic:='0' ;
signal count: integer := 1;
begin
process(clock) -- gives error on this line(line 21: Signal count cannot be synthesized, bad synchronous description.)
begin
if (count = 50000) then
clock1 <= not clock1;
count <= 1;
if (rising_edge (clock)) then
count <= count +1;
end if;
end if;
end process ;
Process(clock1) -- gives error on this line(line 32: Signal lag cannot be synthesized, bad synchronous description.)
begin
lag <= delay;
if (lag = 0) then
delayF<='1';
if (rising_edge(clock1)) then
lag<= lag-1 ;
end if;
end if;
end process;
end Behavioral;