[SOLVED] Getting each output twice from LFSR

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/*------------------------------------------*/
module lfsr (clock, reset, out);
  
  input clock, reset;
  output [31:0] out;
  
  reg [31:0] temp;
  wire newbit;
  
  xor (newbit,temp[0],temp[10],temp[30],temp[31]);
  
  initial
  temp = 32'hffffffff;
  
  always @(posedge clock)
  begin
    temp <= {newbit,temp[31:1]};
  end
  
  assign out = temp;
     
endmodule
 
/*------------------------------------*/
 
 
//Stimulus
 
module lfsrstimulus;
  reg CLOCK, RESET;
  wire [31:0] OUT;
  
  lfsr l1 (CLOCK, RESET, OUT);
  
  initial
  $monitor($time, "Clock = %b, Output = %b\n", CLOCK,OUT);
  
  initial
  begin
  CLOCK = 1'b1;  
  forever #10 CLOCK = ~CLOCK;
  end
  
  initial
  #100 $finish;
  
endmodule
 
/*--------------------------------------------*/

Code Verilog - [expand]
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@(posedge CLOCK) $display("%t, Output = %b\n", $time, OUT);