FPGAwarrior
Newbie level 5
I am building from existing core VHDL code. It is using two GPIOS for all the INs and OUTs. Initially one bank was IN and the other OUT. As my project made me create more complex PCBs, I had to define the GPIOs as inout.
Here is a reduced form of my code:
Now for my testbench code:
When I run the simulation in ModelSim, I get the following:
How do I avoid these warnings?
Here is a reduced form of my code:
Code:
entity s_k_top is
port(
gpio_1_inout : inout std_logic_vector(35 downto 0); --
gpio_0_inout : inout std_logic_vector(35 downto 0);
);
signal gate : unsigned(5 downto 0):= to_unsigned(0, 6); -- used as a reference to trigger processes.
begin
-- several processes and pages of code...
-- One process is the gate keeper which uses a value named "gate" to call some processes sequentially.
-- Definition of primitives
gpio_1_inout(0) <= tst_led(13) when gate >= 3 else 'Z';-- pin1 -- I want all of my GPIOs to start as input upon power-on.
gpio_1_inout(1) <= tst_led(14) when gate >= 3 else 'Z';-- pin2
gpio_0_inout(34) <= B3 when gate >= 3 else 'Z';-- pin39 B3
gpio_0_inout(35) <= pf_shutter when gate >= 3 else 'Z';-- pin40 B2Now for my testbench code:
Code:
entity tb_s_k_top is
end tb_s_k_top;
architecture tb of tb_s_k_top is
signal gpio_0_inout : std_logic_vector (35 downto 0);
signal gpio_1_inout : std_logic_vector (35 downto 0);
begin
uut : entity work.s_k_top
port map (CLK => CLK,
gpio_0_inout => gpio_0_inout,
gpio_1_inout => gpio_1_inout,
);
end tbHow do I avoid these warnings?
Last edited by a moderator: